L-DSP片上调试电路的设计与实现  

Design and Implementation of L-DSP On-chip Debug Circuit

作　　者：白创 李帆 汪东 BAI Chuang;LI Fan;WANG Dong(School of Physics&Electronic Science,Changsha University of Science&Technology,Changsha 410114,China;Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering,Changsha 4100114,China;Hunan Great-Leo Microelectronic Co,Ltd,Changsha 410005,China)

机构地区：[1]长沙理工大学物理与电子科学学院,湖南长沙410114 [2]柔性电子材料基因工程湖南省重点实验室,湖南长沙410114 [3]湖南毂梁微电子有限公司,湖南长沙410005

出　　处：《湖南大学学报（自然科学版）》2020年第8期69-73,共5页Journal of Hunan University:Natural Sciences

基　　金：湖南省教育厅科学研究资助项目(18B164)。

摘　　要：针对L-DSP的调试需求,设计了一种基于JTAG接口的片上调试电路.该调试电路实现了存储资源访问、CPU流水线控制、硬件断点/观察点、参数统计等调试功能.相对于传统调试方式,本文电路通过增加DT-DMA模块,实现数据在外设与内存之间直接传输,极大地提升了调试效率.调试电路在0.18μm CMOS工艺下实现,面积为167 234.76μm2,功耗为8.89mW.同时,调试电路与L-DSP全芯片在FPGA下进行验证,结果表明,该调试电路调试功能完整且DT-DMA传输调试数据的速度是CPU传输的3倍.According to the debug requirements of L-DSP,an on-chip debug circuit based on JTAG interface is proposed in this paper,which implements the debug functions such as storage resource access,CPU pipeline control,hardware breakpoint/observation point,and parameter statistics.Compared with the traditional debug mode,the proposed debug circuit realizes the direct transmission of data between peripherals and memory by adding a DT-DMA module,which greatly improves the debug efficiency.The proposed circuit is designed in a 0.18μm CMOS process with an area of 167234.76μm^2 and a power consumption of 8.89 mW.And the proposed circuit and L-DSP are verified under the FPGA.The results show that the proposed circuit has complete debug functions and the rate of DT-DMA for transferring debug data is three times faster than that of the CPU.

关 键 词：调试 片上调试 JTAG接口 DT-DMA DMA操作 

分 类 号：TN495[电子电信—微电子学与固体电子学]