低复杂度高阶APSK解映射方法与实现结构  

Low-complexity demapping algorithm and implementation architecture for high-order APSK

作　　者：李慧 彭昱 韩昌彩 陈为刚 Li Hui;Peng Yu;Han Changcai;Chen Weigang(School of Microelectronics,Tianjin University,Tianjin 300072,China)

机构地区：[1]天津大学微电子学院,天津300072

出　　处：《电子测量与仪器学报》2020年第6期109-116,共8页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金(61671324)资助项目。

摘　　要：针对高阶幅度相移键控(amplitude phase shift keying,APSK)解映射复杂度,不易硬件实现的问题,提出了一种低复杂度的APSK解映射方案及电路实现结构。具体而言,基于Max-Log-MAP算法,分析APSK星座图对称性并进行区域划分,对落到每个区域的接收符号比特软信息计算进行化简,得到具有低计算量的解映射公式。进一步,利用简化后每个比特软信息计算公式的特点,设计了软信息计算电路结构并在现场可编程门阵列(field programmable gate array,FPGA)硬件平台上进行了性能测试。测试结果表明,信噪比为14 dB时,利用简化方法实现的APSK解映射电路可实现10-5的误比特率(bit error rate,BER),与传统解映射算法性能接近,且具有较低的硬件资源消耗。Aiming at the problem of high-order amplitude phase shift keying(APSK)demapping complexity and difficult hardware implementation,a low-complexity APSK demapping scheme and circuit implementation architecture are proposed.Specifically,the constellation map is divided into regions based on the analysis of symmetry.Then,based on the Max-Log-MAP algorithm,the bit soft information of the received symbols falling into each region is calculated and simplified,thereby obtaining a formula with a low calculation amount for calculating the soft information.Furthermore,using the characteristics of the simplified soft information calculation formula for each bit,the soft information calculation circuit architecture is designed and its performance is tested on the field programmable gate array(FPGA)hardware platform.Test results show that the APSK demapping circuit using the proposed simplified method can achieve a bit error rate(BER)of 10-5 when the signal-to-noise ratio(SNR)is 14 dB,which is close to the performance of the traditional demapping algorithm and has lower hardware resource consumption.

关 键 词：幅度相移键控 软解映射 现场可编程门阵列 

分 类 号：TN911.3[电子电信—通信与信息系统]