基于相位内插的小数分频器  

Fractional-N Frequency Divider Based on Phase Interpolation

作　　者：李璇 周明珠 LI Xuan;ZHOU Mingzhu(Institute of Microelectronic CAD,Hangzhou Dianzi University,Hangzhou Zhejiang 310018,China)

机构地区：[1]杭州电子科技大学微电子CAD研究所,浙江杭州310018

出　　处：《杭州电子科技大学学报（自然科学版）》2020年第4期13-19,共7页Journal of Hangzhou Dianzi University：Natural Sciences

基　　金：国家自然科学基金资助项目(61774035)。

摘　　要：为了实现真小数分频,设计一种高移相精度、高线性度、低功耗的,与CMOS集成电路工艺兼容的360°相位内插电路。基于SMIC 55 nm CMOS工艺进行电路及版图设计,Cadence软件仿真结果表明:频率为2.4 GHz正弦信号在1.2 V供电电压下,其相位内插精度小于2 ps;输入信号幅度为20 mV时,输出信号幅度可达98 mV,具有较小的相位误差与良好的增益和线性度。相位内插器、相位控制器与整数分频器共同构成小数分频器,实现真小数分频,当输入信号频率为2.4 GHz,整数分频为4,小数位为0.246时,可实现对输入信号的3.754分频,仿真输出信号平均频率为638.96 MHz,误差为0.36 MHz。In order to achieve true fractional-n frequency division, a 360° phase interpolation circuit with high phase shift accuracy, high linearity, and low power consumption is designed which is compatible with CMOS integrated circuit technology. Based on the SMIC 55 nm CMOS process for circuit and layout design, Cadence software simulation results show that the phase interpolation accuracy of a sinusoidal signal at a frequency of 2.4 GHz is less than 2 ps at a supply voltage of 1.2 V;when the input signal amplitude is 20 mV, the output signal amplitude can reach 98 mV, with small phase error, good gain and linearity. The phase interpolator, the phase controller and the integer divider together form a fractional divider to achieve true fractional-n frequency division. When the input signal frequency is 2.4 GHz, the integer frequency division is 4, and the decimal place is 0.246, the input signal can be divided by 3.754. The average frequency of the simulated output signal is 638.96 MHz with an error of 0.36 MHz.

关 键 词：相位内插器 移相器 真小数分频器 线性度 

分 类 号：TN772[电子电信—电路与系统]