160 GHz三级堆栈式CMOS功率放大器的设计  

Design of a 160 GHz Three-stage Stacked CMOS Power Amplifier

作　　者：陈天伟 毛陆虹 谢生 刘一波 Chen Tianwei;Mao Luhong;Xie Sheng;Liu Yibo(School of Electrical and Information Engineering,Tianjin University,Tianjin 300072,China)

机构地区：[1]天津大学电气自动化与信息工程学院,天津300072

出　　处：《南开大学学报（自然科学版）》2020年第4期63-66,92,共5页Acta Scientiarum Naturalium Universitatis Nankaiensis

基　　金：国家自然科学基金重点项目(61331003);广西精密导航技术与应用重点实验室开放基金(DH201513)。

摘　　要：在40 nm标准CMOS工艺下,使用堆栈式结构设计了160 GHz的伪差分式三级功率放大器,并且应用了中和电容技术提升了其增益与稳定性.其中,级间匹配与输入输出Balun使用了片上变压器,从而减小了匹配损耗,并且提升了最终的带宽.讨论了在伪差分堆栈式结构中使用中和电容的影响与解决方案.仿真结果表明:功放在160 GHz时达到最大增益11.4 dB,3 dB带宽达到24.9 GHz,饱和输出功率达到4.9 dBm,功耗为84.5 mW.对比传统的共源级和共源共栅结构,堆栈式结构也可以应用于毫米波电路,并且提升了功放的性能.A 160 GHz three-stage stacked pseudo-differential power amplifier was designed in standard 40 nm CMOS.Capacitive cross-coupling neutralization was optimized,which results in improvement of gain and stability.And on-chip transformers and baluns were used in inter-stage,input and output matching to reduce the matching loss,then enhance the final bandwidth.Effects and solutions were discussed to apply neutralization capacitors in a pseudo-differential stack architecture.The power amplifier achieves a small-signal gain of 11.4 dB at 160 GHz with a 3 dB bandwidth of 24.9 GHz,saturated output power of 4.9 dBm,and power consumption of 84.5 mW.Compared to traditional common-source and cascode PAs,Stacked PA,which has superior performance,is more suitable for millimeter-wave circuit.

关 键 词：堆栈式 毫米波 中和电容 变压器 功率放大器 

分 类 号：TN431.1[电子电信—微电子学与固体电子学]