基于自适应环路滤波算法的全数字锁相环设计与分析  

Design and analysis of the all-digital phase-locked loop based on adaptive loop filtering algorithm

作　　者：周郭飞 杨宏[1] 杨延峰 ZHOU Guo-fei;YANG Hong;YANG Yan-feng(First Research Institute of The Ministry of Public Security,Beijing 100044,China)

机构地区：[1]公安部第一研究所,北京100044

出　　处：《微电子学与计算机》2020年第9期62-67,72,共7页Microelectronics & Computer

摘　　要：环路滤波器是全数字锁相环中重要的模块,对环路的许多性能都有着重要的影响.为了加快锁定时间的同时降低带内噪声,本文提出了一种适用II型全数字锁相环的自适应环路滤波算法.该算法预先选择多组对应带宽由大到小的环路滤波参数.在跟踪过程中,根据环路的状态依次在特定的时刻切换参数,并对因切换导致频率控制字跳变进行补偿.本文首先证明了自适环路滤波器的可行性,然后给出了算法的实现流程,最后采用Verilog-A语言在HSPICE中对上述算法进行了仿真实验.实验结果表明采用本文提出的自适应环路滤波,ADPLL锁定时间仅仅略大于第一组参数对应的锁定时间,而其锁定后的相位噪声与最后一组参数的相同.The digital Loop filter is a key module in all digital phase locked loop(ADPLL)and has an important impact on the performance of the loop.In order to shorten the settling time and reduce the in-band phase noise,this paper proposes a type II ADPLL adaptive loop filtering algorithm.To implement the algorithm,several sets of loop filter parameters with large to small bandwidth are pre-selected.In the tracking process,the algorithm will switch those parameters orderly at a special time according to the state of the loop,and the non-ideal jump of frequency control word caused by the switching is compensated at the same time.Finally,this paper built a Type II ADPLL with three sets of loop filtering parameters in HSPICE using Verilog-A language,and simulated the algorithm.The simulation results show that the total lock time of the loop is only slightly larger than that of the first set of parameters,and the phase noise characteristic after locking is the same as the last set of parameters.

关 键 词：数字环路滤波器 锁定时间 相位噪声 全数字锁相环 

分 类 号：TN402[电子电信—微电子学与固体电子学]