基于摆幅恢复传输管逻辑的高性能全加器设计  

High-performance full adder design based on SRPL

作　　者：韩金亮 张跃军[1] 温亮 张会红[1] HAN Jin-liang;ZHANG Yue-jun;WEN Liang;ZHANG Hui-hong(Faculty of Electrical Engineering and Computer Science,Ningbo University,Ningbo 315211,China;Department of Electronic Technology,China Coast Guard Academy,Ningbo 315211,China)

机构地区：[1]宁波大学信息科学与工程学院,宁波315211 [2]中国人民武装警察部队海警学院电子技术系,宁波315211

出　　处：《工程科学学报》2020年第8期1065-1073,共9页Chinese Journal of Engineering

基　　金：国家自然科学基金资助项目(61871244,61874078);浙江省自然科学基金资助项目(LY18F040002);宁波大学王宽诚幸福基金;宁波大学教学研究资助项目(JYXMXYB201934);宁波大学研究生科研创新资助基金(2019SRIP1335)。

摘　　要：为了降低硬件开销,越来越多的加法器电路采用传输管逻辑来减少晶体管数量,同时导致阈值损失、性能降低等问题.本文通过对摆幅恢复逻辑与全加器电路的研究,提出一种基于摆幅恢复传输管逻辑(Swing restored pass transistor logic,SRPL)的全加器设计方案.该方案首先分析电路的阈值损失机理,结合晶体管传输高、低电平的特性,提出一种摆幅恢复传输管逻辑的设计方法;然后,采用对称结构设计无延时偏差输出的异或/同或电路,利用MOS管补偿阈值损失的方式,实现异或/同或电路的全摆幅输出;最后,将异或/同或电路融合于全加器结构,结合4T XOR求和电路与改进的传输门进位电路实现摆幅恢复的高性能全加器.在TSMC 65 nm工艺下,本文采用HSPICE仿真验证所设计的逻辑功能,与文献相比延时降低10.8%,功耗延时积(Power-delay product,PDP)减少13.5%以上.The adder circuit is the core component of the high-performance system-on-chip(SoC).It is also important in image and voice encryption.The full adder circuit is a basic unit with a very high reuse rate among all the units.Therefore,the design of an adder with high energy efficiency is of great significance for the optimization of digital circuit systems.In recent years,numerous researchers have studied the design of advanced adder circuits,which are characterized by high speed and low power consumption.To reduce the hardware overhead,an increasing number of adder circuits utilize the transmission tube logic to reduce the number of transistors.However,this method also brings about several negative effects,such as threshold loss and performance degradation.In this paper,by studying the swing recovery logic and full adder circuit,we proposed a full adder design scheme based on swing restored pass-transistor logic(SRPL).First,the threshold loss mechanism of the circuit was analyzed,and the characteristics of the high-efficiency transmission of high-level and low-level transistors were considered;then the design method of the swing recovery transmission tube logic was developed.We used a symmetric structure to design an XOR/XNOR circuit without delay deviation output.The two-shot MOS tube was used to compensate the threshold loss to realize the full swing output of the XOR/XNOR circuit.Finally,we fused the designed XOR/XNOR circuit to the full adder structure and used the 4 T XOR sum circuit and the improved transmission gate carry circuit to implement the high-performance full adder for swing recovery.In the TSMC 65 nm process,the logic function of our method was verified by HSPICE simulation.Compared with the conventional approach,the delay is reduced by 10.8%,and the power-delay product(PDP)is reduced by more than 13.5%.The design method of low delay and full swing output of the SRPL circuit can be further applied to the design of other logic circuits,further promoting the practical process of the SRPL circuit.

关 键 词：异或/同或 摆幅恢复 高性能全加器 阈值损失 全摆幅 

分 类 号：TN702[电子电信—电路与系统]