一种10MHz带宽70dB动态范围连续时间Sigma-Delta调制器  

A Continuous-Time Sigma-Delta Modulator with 10 MHz Bandwidth and 70 dB Dynamic Range

作　　者：陈凯让 王友华[1] 赵霜叶 黄兴发[1] 刘建伟 卢涛静 CHEN Kairang;WANG Youhua;ZHAO Shuangye;HUANG Xingfa;LIU Jianwei;LU Taojing(Science and Technology on Analog Integrated Circuit Laboratory,Chongqing400060,P.R.China;Chongqing Giga Chip Technology Co.,Ltd.,Chongqing401334,P.R.China)

机构地区：[1]模拟集成电路国家重点实验室,重庆400060 [2]重庆吉芯科技有限责任公司,重庆401334

出　　处：《微电子学》2020年第4期459-464,共6页Microelectronics

基　　金：模拟集成电路国家重点实验室基金资助项目(61428020106)。

摘　　要：介绍了4阶反馈型连续时间Sigma-Delta调制器从顶层到底层的详细设计过程。采用数字置乱技术,降低失配对输出杂散的影响,使失配产生的谐波被转换为噪声,并被移出通带外。将谐振腔内嵌于调制器环路中,以改善带内信噪比。采用三级前馈型放大器,调制器具备更高的能效。该调制器基于65 nm CMOS工艺设计并流片。测试结果表明,在时钟频率为614.4 MHz、信号带宽为10 MHz时,调制器的SNDR为70.1 dB,动态范围达70 dB。功耗为77 mW。该调制器芯片的内核面积为4.50 mm^2。A detailed top to down design progress of a fourth-order feedback mode continuous-time sigma-delta modulator was introduced. The digital shuffling method was used to eliminate the effect on the output spurious caused by the mismatch. Due to the calibration, the harmonic generated by the mismatch was transformed to noise and shaped to the out of the signal band. Aiming to further improve the SNR in the signal bandwidth, the resonator was embedded into the modulator. A power efficiency modulator was obtained by using the three-stage feed-forward amplifier. Finally, the modulator was designed and fabricated in a 65 nm CMOS process. The measurement results showed that the modulator achieved a peak SNDR of 70.1 dB at 10 MHz bandwidth with a sampling frequency of 614.4 MHz while obtaining a dynamic range up to 70 dB. The power consumption was 77 mW. The core area of the modulator chip was 4.50 mm^2.

关 键 词：连续时间Sigma-Delta调制器 数字置乱 前馈型放大器 谐振腔 

分 类 号：TN406[电子电信—微电子学与固体电子学]