一种13.22 fJ 12位200 MS/s电流舵DAC  

A 13.22-fJ 12-bit 200-MS/s Current Steering DAC

作　　者：张帅 张润曦[1] 石春琦[1] ZHANG Shuai;ZHANG Runxi;SHI Chunqi(Institute of Microelectronic Circuits and Systems,East China Normal University,Shanghai 200241,P.R.China)

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200241

出　　处：《微电子学》2020年第4期465-469,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61306034)。

摘　　要：采用55 nm CMOS工艺,设计了一个12位电流舵DAC。根据Matlab建模结果,确定电流舵DAC采用"6+3+3"的分段结构,这种分段结构使得版图面积和微分非线性(DNL)均较小;共源共栅电流源有效提高了电流源的输出阻抗;开关结构中的MOS电容减小了信号馈通效应的影响;与电流源栅端相连的电容稳定了电流源的偏置电压。基于以上特点,在未采用静态和动态校准技术的情况下,电流舵DAC能得到较好的性能指标。后仿真结果表明,采样率为200 MS/s、输入信号频率为1.07 MHz时,在25℃、TT工艺角下,该DAC的无杂散动态范围(SFDR)为78.62 dB,DNL为0.5 LSB,积分非线性(INL)为0.8 LSB。该电流舵DAC的电源电压为1.2 V,功耗为18.43 mW,FOM为13.22 fJ。Based on a 55 nm CMOS technology, a 12-bit current steering digital-to-analog converter(DAC) was designed. According to the results of the Matlab modeling, the current steering DAC was doubly-segmented "6+3+3" architecture, which had small area and DNL. The cascode current source provided high output impedance. The MOS used as capacitance in the switch and current source cell could reduce the signal feedthrough effect. The capacitance connected to the gate of the current source MOS could keep the bias voltage stable. With these features, the current steering DAC had obtained high performance without static and dynamic calibration techniques. The post-simulation results showed that the intrinsic accuracy DAC provided 78.62 dB spurious free dynamic range(SFDR) with 1.07 MHz input signal at 200 MHz sampling clock frequency, TT corner and 25 ℃. The integral non-linearity(INL) and the differential non-linearity(DNL) were 0.8 and 0.5 least significant bit(LSB), respectively. The 1.2 V power supply was used by the proposed DAC. The total power consumption was 18.43 mW. The figure of merit(FOM) of the proposed DAC was 13.22-fJ.

关 键 词：电流舵DAC 共源共栅电流源 无杂散动态范围 FOM 

分 类 号：TN792[电子电信—电路与系统]