一种低功耗高PSRR CMOS基准电压源  

A Low Power and High PSRR CMOS Voltage Reference

作　　者：符征裕 段吉海[1] 韦胶二 孔令宝 崔鹏 FU Zhengyu;DUAN Jihai;WEI Jiaoer;KONG Lingbao;CUI Peng(Guangxi Key Lab.of Precision Naviga.Technol.and Applic.,Guilin Univ.of Elec.Technol.,Guilin,Guangxi 541004,P.R.China)

机构地区：[1]桂林电子科技大学广西精密导航技术与应用重点实验室,广西桂林541004

出　　处：《微电子学》2020年第4期477-481,共5页Microelectronics

基　　金：广西自然科学基金资助项目(2017JJA170452y);广西精密导航技术与应用重点实验室主任基金资助项目(DH201806);广西桂林电子科技大学研究生科研创新项目(2019YCXS023)。

摘　　要：提出了一种采用新颖负温漂系数电流源补偿结构的高性能基准电压源。利用工作在亚阈值区的两个MOS管的栅源电压差与工作在线性区的MOS管的漏电流关系,产生补偿电流,使输出电压对温度不敏感。提出的负温漂电流源结构没有使用传统大电阻,不仅保证了低功耗,还有效减小了芯片面积。采用共源共栅的电流源结构,提高了电源抑制比。基于TSMC 0.18μm CMOS工艺进行设计仿真。仿真结果表明,在-35℃~150℃范围内,温漂系数为8.3×10^-6/℃。电源电压为1.3~3.3 V时,电压调整率为0.21%,电源抑制比为-81.2 dB@100 Hz,功耗仅为184.7 nW。芯片面积为0.006 mm2。A high performance voltage reference with a novel negative temperature coefficient current source compensation structure was presented. The output voltage variation due to temperature was minimized by using the relationship between the drain current of a transistor working in linear region and the gate-source voltage difference of two transistors working in sub-threshold region. Instead of the large resistance in traditional circuits, the negative temperature current source structure was used to reduce significantly the chip area with low power consumption. A cascode current mirror was used to increase the power supply rejection ratio(PSRR). The voltage reference was designed and simulated in TSMC 0.18 μm CMOS process. The simulation results demonstrated that the temperature coefficient of the voltage was 8.3 ×10^-6/℃ at the temperarture range of-35 ℃ to 150 ℃. The line sensitivity was 0.21% at the supply voltage range of 1.3 to 3.3 V, and the PSRR was-81.2 dB at 100 Hz. The power consumption was only 184.7 nW, and the chip area was 0.006 mm2.

关 键 词：低功耗 温漂系数 电流模式 电源抑制比 

分 类 号：TN432[电子电信—微电子学与固体电子学]