一种高速串行信号线性均衡电路  

A Linear Equalization Circuit for High Speed Serial Signal

作　　者：兰雨娇 侯伶俐 岳宏卫[1] 韦雪明[1] LAN Yujiao;HOU Lingli;YUE Hongwei;WEI Xueming(Guangxi Key Laboratory of Wireless Broadband Communication and Signal Processing,Guilin,Guangxi 541004,P.R.China;Chengdu SINO Microelectronics Technology Co.,Ltd.,Chengdu610041,P.R.China)

机构地区：[1]桂林电子科技大学广西无线宽带通信与信号处理重点实验室,广西桂林541004 [2]成都华微电子科技有限公司,成都610041

出　　处：《微电子学》2020年第4期514-520,共7页Microelectronics

基　　金：广西无线宽带通信与信号处理重点实验室主任基金资助项目(GXKL06190110);桂林电子科技大学研究生教育创新计划资助项目(2018XWYJ18);桂林电子科技大学研究生课程建设项目(YKC201703)。

摘　　要：设计了一种高速串行信号连续时间线性均衡器。采用有源电感负载结构,结合高频与全频通路信号求和技术来实现高速串行信号均衡。电路具有面积小、功耗低、利于集成等优点。采用65 nm CMOS工艺进行设计,1.2 V电源供电,可对经过80 cm长的衰减信道、且传输速率为14 Gbit/s的信号进行补偿,实现6.24 dB@10.96 GHz的补偿。该均衡器将输出端信号眼图水平方向抖动减小至0.25UI,功耗数据率比低至0.399 mW·s/Gbit,设计版图面积为0.09 mm^2。A continuous-time linear equalizer for high speed serial signal was designed on the basis of active inductance load structure. The equalizer was complemented by the mixing technology of high frequency signal branch and full frequency signal branch. It featured small area and low power consumption, and was easy to integrate on one chip. The equalizer was designed in a 65 nm CMOS technology with 1.2 V power supply, and it could provide 6.24 dB @10.96 GHz attenuation compensation for transmission signals which transmitted up to 14 Gbit/s in 80 cm attenuation channel. Observed from the output signal eye diagram, the equalizer’s output jitter at horizontal direction was reduced to 0.25UI, the ratio of power dissipation and data rate was as low as 0.399 mW·s/Gbit, and the corresponding layout area was 0.09 mm^2.

关 键 词：有源电感负载 高速串行信号 线性均衡器 信道均衡 眼图 

分 类 号：TN432[电子电信—微电子学与固体电子学]