源端射频干扰下CMOS数字电路的时序失效机理  

Timing Failure Mechanism of CMOS Digital Circuits Under Radio Frequency Interference on the Supply

作　　者：农姗珊 杨斯媚 粟涛 NONG Shanshan;YANG Simei;SU Tao(School of Electronics and Information Technology,Sun Yat-Sen University,Guangzhou510006,P.R.China)

机构地区：[1]中山大学电子与信息工程学院,广州510006

出　　处：《微电子学》2020年第4期536-542,共7页Microelectronics

基　　金：国家自然科学基金资助项目(61471402)。

摘　　要：当前CMOS数字芯片设计流程缺少对电路电磁抗扰性的检验。大幅电磁干扰会导致数字电路出现电路失效,但电路失效的原因以及电路失效与幅度和频率等干扰参数的关系尚不清楚。针对这一问题,详细研究了源端射频干扰下CMOS数字电路的工作状态。通过给出失效与干扰参数的关系的基本理论,得到CMOS数字电路在受扰情况下的失效原因。结果表明,时序错误是大幅电磁干扰引起CMOS电路失效的主要原因。电路失效可通过电路路径延时的漂移和抖动来解释,漂移和抖动与电磁干扰的幅度和频率存在特定关系,因此时序失效是可预测的。基本理论所描述的失效规律可作为EDA工具的原理,用于芯片设计早期阶段对电路的抗扰性检验。At present, the design process of CMOS digital chip lacked the test of circuit electromagnetic immunity. However, the reason of circuit failure and the relationship between circuit failure and interference parameters such as amplitude and frequency were not clear. In order to solve this problem, the working state of CMOS digital circuit under the source RF interference was studied in detail. By giving the basic theory of the relationship between failure and interference parameters, the failure reason of CMOS digital circuit in the case of being disturbed was obtained. The results showed that timing error was the main cause of CMOS circuit failure caused by large electromagnetic interference. The circuit failure could be explained by the shift and jitter of the circuit path delay. There was a specific relationship between the shift and jitter and the amplitude and frequency of electromagnetic interference, so the timing failure was predictable. The failure rule described in the basic theory could be used as the principle of EDA tool to test the circuit immunity in the early stage of chip design.

关 键 词：数字集成电路 电磁干扰 时序收敛 失效机理 

分 类 号：TN432[电子电信—微电子学与固体电子学]