用于14位210MS/s电荷域ADC的4.5位子级电路  

4.5 bit Sub-stage Circuit for 14 bit 210 MS/s Charge-domain ADC

作　　者：薛颜[1] 于宗光[1] 陈珍海[1,2,3] 魏敬和 钱宏文[1] XUE Yan;YU Zongguang;CHEN Zhenhai;WEI Jinghe;QIAN Hongwen(No.58 Research Institute,China Electronic Technology Group Corporation,Wuxi 214035,China;School of Information Engineering,Huangshan University,Huangshan 245041,China;Engineering Technology Research Center of Intelligent Microsystems AnHui Province,Huangshan 245041,China)

机构地区：[1]中国电子科技集团第五十八研究所,无锡214035 [2]黄山学院信息工程学院,黄山245041 [3]智能微系统安徽省工程技术研究中心,黄山245041

出　　处：《电子与信息学报》2020年第9期2312-2318,共7页Journal of Electronics & Information Technology

摘　　要：该文提出了一种用于高速高精度电荷域流水线模数转换器(ADC)的电荷域4.5位前端子级电路。该4.5位子级电路使用增强型电荷传输(BCT)电路替代传统开关电容技术流水线ADC中的高增益带宽积运放来实现电荷信号传输和余量处理,从而实现超低功耗。所提4.5位子级电路被运用于一款14位210 MS/s电荷域ADC中作为前端第1级子级电路,并在1P6M 0.18 mm CMOS工艺下实现。测试结果显示,该14位ADC电路在210 MS/s条件下对于30.1 MHz单音正弦输入信号得到的无杂散动态范围为85.4 dBc,信噪比为71.5 dBFS,ADC内核面积为3.2 mm^2,功耗仅为205 mW。A 4.5 bit sub-stage circuit for high speed high precision charge domain pipelined Analog-to-Digital Converter(ADC)is proposed.Instead of the high-performance opamps used in traditional switched-capacitor pipelined ADCs,charge transfer and residue charge calculation is realized with Boosted Charge Transfer(BCT)circuit in the proposed 4.5 bit sub-stage.Therefore,the power consumption of the 4.5 bit sub-stage circuit can be reduced remarkably.The proposed 4.5 bit sub-stage circuit is used as the 1st stage circuit for a 14 bit 210 MS/s charge domain pipelined ADC and realized in a 1P6M 0.18 mm CMOS process.Test results show the 14 bit 210 MS/s ADC achieves the signal-to-noise ratio of 71.5 dBFS and the spurious free dynamic range of 85.4 dB,with 30.1 MHz input single tone signal at 210 MS/s,while the ADC core consumes the power consumption of 205 mW and occupies an area of 3.2 mm^2.

关 键 词：流水线模数转换器 电荷域 子级电路 低功耗 

分 类 号：TN47[电子电信—微电子学与固体电子学]