UHF RFID电子标签芯片低功耗设计及时钟树优化  

Low Power Design and Clock Tree Optimization for UHF RFID Tags

作　　者：徐一 胡旭 冯曦 胡毅 唐晓柯 XU Yi;HU Xu;FENG Xi;HU Yi;TANG Xiaoke(State Grid Key Laboralory of Power Industrial Chip Design and Analysis Technology,Bejing Smarl chip Microelectronics Technology Co.,LId.,Bejing,100192,CHN;Bejing Engineering Research Center of High-reliability IC with Porwer Industrial Grade,Beijing Smart chip Microelectronics Technology Co,Lld.,Beijing,100192,CHN)

机构地区：[1]北京智芯微电子科技有限公司,国家电网公司重点实验室电力芯片设计分析实验室,北京100192 [2]北京智芯微电子科技有限公司,北京市电力高可靠性集成电路设计工程技术研究中心,北京100192

出　　处：《固体电子学研究与进展》2020年第4期311-316,共6页Research & Progress of SSE

基　　金：国家电网科技项目(546816180010)。

摘　　要：超高频射频识别标签(UHF RFID)的一个重要指标是工作距离,而提高工作距离的有效方法是降低标签工作功耗。针对一款基于EPC Class-1 Generation-2/ISO18000-6C协议的RFID芯片,提出一种数字后端设计中时钟树动态功耗的优化方法,该方法可以在已完成布局布线的版图上进一步降低动态功耗。在时钟频率1.28MHz、返回频率170 kHz条件下,功耗仿真结果由1.58μW降低到1.357μW。已在TSMC 0.18μm工艺下流片,室温情况下准备阶段样品测试结果数字功耗为0.752 5μW,与后仿真结果0.750 0μW接近,实测激活灵敏度为-18.5 dBm。An important performance specification of UHF RFID(Ultra-high Frequency Radio Frequency Identification)is the operating distance,which can be extended by reducing the power consumption of tag. In this paper,an RFID chip based on EPC Class-1 Generation-2/ISO18000-6C protocol is presented. An optimization method for dynamic power consumption of clock tree in digital back-end design is proposed. This method can further reduce the dynamic power consumption on the completed layout. Under the condition of 1.28 MHz clock frequency and 170 kHz back scatter-link frequency,the simulation results of power consumption decreased from 1.58 μW to 1.357 μW. A chip has been taped out in the TSMC 0.18 μm process,and the sample test results of the digital power consumption is 0.752 5 μW at room temperature,which is close to the post simulation result of 0.750 0μW. The sensitivity is -18.5 dBm.

关 键 词：低功耗 时钟树 物理设计 动态功耗优化 

分 类 号：TN432[电子电信—微电子学与固体电子学]