低功耗X86指令译码部件的设计与实现  

Design and Implementation of Low Power X86 Instruction Decoder

作　　者：张骏 田泽[1,2,3] 任向隆 许宏杰[1,2,3] 刘航 ZHANG Jun;TIAN Ze;REN Xiang-long;XU Hong-jie;LIU Hang(Xi'an Xiangteng Micro-electronic Technology Co.,Ltd.,Xi'an 710068,China;Xi'an Aeronautics Computing Technique Research Institute,AVIC,Xi'an 710068,China;Key Laboratory of Aviation Science and Technology on Integrated Circuit and Micro-system Design,Xi'an 710068,China)

机构地区：[1]西安翔腾微电子科技有限公司,陕西西安710068 [2]航空工业西安航空计算技术研究所,陕西西安710068 [3]集成电路与微系统设计航空科技重点实验室,陕西西安710068

出　　处：《航空计算技术》2020年第5期98-102,共5页Aeronautical Computing Technique

基　　金：核高基重大专项项目资助(2016ZX01012101-004)。

摘　　要：随着处理器设计技术和半导体制造工艺的进步,芯片的规模和复杂度急剧增大,不断提升的功耗密度对系统工作的可靠性和稳定性造成很大影响,“功耗墙”已经成为提升处理器性能的最大障碍。介绍了低功耗设计的基本原理,结合X86指令集的特点,设计了一种X86指令译码器,并在体系结构层次上,提出从指令预取队列和译码队列两个不同角度对X86指令译码器进行低功耗设计的方法。基于SMIC 180 nm CMOS工艺,采用Synopsys DC工具进行了综合实现,并对译码器低功耗设计效果进行了评估。结果表明,在几乎不影响速度和面积的前提下,指令译码器关键数据通路寄存器平均翻转率降低了17.16%。With the fast development of microprocessor design and semiconductor fabrication,The chip size and complexity increase rapidly.The increasing power density impacts the system stability and reliability seriously.“Power wall”has already being the biggest obstruction to upgrade the performance of microprocessor.This paper presents the low power design techniques principle firstly,and then,combined with the characteristics of x86 instruction set,proposes a low power instruction decoder design by optimizing the instruction pre-fetching strategy and decoded instruction FIFO at architecture level.In succession,the proposed low power instruction decoder is implemented by using synopsis DC tool based on SMIC 180 nm CMOS technology.As a result,the average key register bits reverse rate in critical path of the proposed low power x86 instruction decoder decreases about 17.16% relative to original decoder,almost without any impact on area and clock frequency.

关 键 词：微处理器 低功耗 指令译码 X86 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]