基于FPGA的低资源极化码SC译码架构研究与实现  

Research and implementation of low resource polar code SC decoding architecture based on FPGA

作　　者：曹蓉 赵德政 郭佳 李家鑫 Cao Rong;Zhao Dezheng;Guo Jia;Li Jiaxin(National Computer System Engineering Research Institute of China,Beijing 100083,China;Intelligence Technology of CEC Co.,Ltd.,Beijing 100083,China)

机构地区：[1]华北计算机系统工程研究所,北京100083 [2]中电智能科技有限公司,北京100083

出　　处：《电子技术应用》2020年第9期74-78,84,共6页Application of Electronic Technique

基　　金：国防基础科研计划资助项目(JCKY2018211C001)。

摘　　要：针对无线传感器网络中对资源消耗及成本敏感的应用场景,研究并提出了一种基于FPGA的低资源极化码连续删除(Successive Cancellation,SC)译码架构。该译码架构采用同级计算单元串行运算,不同级计算单元并行运算,不同组译码数据并行处理的方式,通过减少计算单元(Processing Element,PE)个数、复用寄存器存储资源提升硬件资源利用率,复用译码延迟提升吞吐率。通过Xilinx xc7vx330t综合结果分析,该译码架构在码长为N=128时译码最高时钟频率为220.444 MHz,吞吐率为89.86 Mb/s,与树型SC译码架构相比,计算单元利用率提升了14.67倍,在主要硬件资源指标查找表(Look-Up-Table,LUT)和触发器(Filp-Flop,FF)上分别节省了74.22%和62.1%。In view of the application scenarios are sensitive to resource consumption and cost in wireless sensor networks,this paper studies and proposes a low resource polar code successive cancellation(SC)decoding architecture based on FPGA.The decoding architecture adopts the serial operation of the same level computing units,the parallel operation of different levels of computing units,and the parallel processing of different groups of decoding data.By reducing the number of processing elements(PE),reusing register storage resources,the architecture improves the utilization of hardware resources,and reusing decoding delay improves the throughput.According to the analysis of the comprehensive results of Xilinx xc7vx330t,when the code length is N=128,the architecture′s highest decoding clock frequency is 220.444 MHz,and the throughput is 89.86 Mb/s.Compared with the tree SC decoding architecture,its utilization ratio of computing unit is increased by 14.67 times.It saves 74.22%and 62.1%on Look-Up-Table(LUT)and Flip-Flop(FF)of main hardware resource indexes respectively.

关 键 词：FPGA 极化码 低资源 计算单元 SC译码架构 

分 类 号：TN911[电子电信—通信与信息系统]