一种应用于阵列TDC的低抖动锁相环设计  

Design of a Low Jitter Phase Locked Loop for Array TDC

作　　者：吴金 孙亚伟[2] 彭杰 郑丽霞[2] 罗木昌 孙伟锋 WU Jin;SUN Ya-wei;PENG Jie;ZHENG Li-xia;LUO Mu-chang;SUN Wei-feng(Southeast University,Nanjing,Jiangsu 210096,China;44th Research Institute of China Electronic Technology Group,Chongqing 400060,China)

机构地区：[1]东南大学微电子学院,江苏南京210096 [2]东南大学,江苏南京216099 [3]中电科技第四十四研究所,重庆400060

出　　处：《电子学报》2020年第9期1703-1710,共8页Acta Electronica Sinica

基　　金：国家重点研发计划(No.2016YFB0400904);国家自然科学基金(No.61805036);江苏省自然科学基金(No.BK20181139);模拟集成电路重点实验室稳定支持项目(No.JCKY2019210C030)。

摘　　要：传统的PLL(Phase Locked Loop)电路受限于环路参数的选定,其相位噪声与抖动特性已经难以满足大阵列、高精度TDC(Time-to-Digital Converter)的应用需求.本文致力于PLL环路带宽的优化选取,采取TSMC 0.35μm CMOS工艺实现了一款应用于TDC的具有低抖动、低噪声特性的锁相环(Phase Locked Loop,PLL)电路,芯片面积约为0.745mm×0.368mm.实际测试结果表明,在外部信号源输入15.625MHz时钟信号的条件下,PLL输出频率可锁定在250.0007MHz,频率偏差为0.7kHz,输出时钟占空比为51.59%,相位噪声为114.66dBc/Hz@1MHz,均方根抖动为4.3ps,峰峰值抖动为32.2ps.锁相环的相位噪声显著降低,输出时钟的抖动特性明显优化,可满足高精度阵列TDC的应用需要.The traditional PLL(Phase Locked Loop)circuit is limited by the selection of loop parameters and its phase noise and jitter characteristics have been difficult to meet the application requirements of large array and high precision TDC(Time-to-Digital Converter).This paper devotes to the optimal selection of PLL loop bandwidth and a PLL circuit with low noise and low jitter characteristics is designed.The chip area is approximately 0.745mm×0.368mm.The actual test results of the chip show that under the condition of external signal source input 15.625MHz clock signal and the PLL output frequency can be locked at 250.0007MHz.The frequency deviation is 0.7kHz.The duty cycle of the output clock is 51.59%and the phase noise is-114.66dBc/[e-mail] RMS jitter of the clock is 4.3ps and the peak-to-peak jitter is 32.2ps.The phase noise of the phase-locked loop is significantly reduced and the jitter characteristics of the output clock are significantly optimized,which can basically meet the application needs of the array TDC.

关 键 词：锁相环 低抖动 相位噪声 

分 类 号：TN911.8[电子电信—通信与信息系统]