基于FPGA集群的脉冲神经网络仿真器设计  

Design of Spiking Neural Network Simulator Based on FPGA Cluster

作　　者：李康 张鲁飞 张新伟 郁龚健 刘家航 吴东 柴志雷[1,2] LI Kang;ZHANG Lufei;ZHANG Xinwei;YU Gongjian;LIU Jiahang;WU Dong;CHAI Zhilei(School of Internet of Things Engineering,Jiangnan University,Wuxi,Jiangsu 214122,China;State Key Laboratory of Mathematical Engineering and Advanced Computing,Wuxi,Jiangsu 214215,China)

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]数学工程与先进计算国家重点实验室,江苏无锡214215

出　　处：《计算机工程》2020年第10期201-209,共9页Computer Engineering

基　　金：国家自然科学基金(61972180);数学工程与先进计算国家重点实验室开放基金(2018A04)。

摘　　要：针对类脑计算系统中NEST脉冲神经网络仿真器运行速度慢和功耗高的问题,设计一种基于现场可编程逻辑门阵列(FPGA)集群的NEST脉冲神经网络仿真器。在改进NEST仿真器结构的基础上,提出漏电流整合放电神经元计算模块的流水线并行架构,实现支持双核双线程和多节点多进程的FPGA集群设计。在皮质层视觉仿真模型上的实验结果表明,与基于Xeon E5-2620和ARM A9平台的NEST仿真器相比,基于FPGA集群的NEST仿真器计算能效和速度分别提升43.93倍、23.54倍和12.36倍、208倍,能为大规模类脑计算系统实现提供技术支持。To address the low running speed and high power consumption of the NEST Spiking Neural Network(SNN)simulators in the brain-like computing systems,this paper proposes a NEST simulator based on Field Programmable Gate Array(FPGA)cluster for SNN.By improving the structure of NEST simulator,a pipeline parallel architecture of the Leaky Integrate and Fire(LIF)neuron calculation module is proposed,which realizes the design of the dual-core dual-thread and multi-node multi-process FPGA cluster.The experimental results of cortical visual simulation model show that the computational energy efficiency of the proposed FPGA-cluster-based NEST simulator is 43.93 times that of the Xeon E5-2620 and 23.54 times that of the ARM A9.The computational speed of the proposed simulator is 12.36 times that of the Xeon E5-2620 and 208 times that of the ARM A9.

关 键 词：类脑计算系统 脉冲神经网络仿真器 现场可编程逻辑门阵列集群 硬件实现 皮质层视觉仿真模型 

分 类 号：TP183[自动化与计算机技术—控制理论与控制工程]