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作 者:Xiao LIANG Huizheng WANG Yifei SHEN Zaichen ZHANG Xiaohu YOU Chuan ZHANG
机构地区:[1]Laboratory of Efficient Architectures for Digital-communication and Signal-processing(LEADS),Southeast University,Nanjing 211100,China [2]National Mobile Communications Research Laboratory,Southeast University,Nanjing 211100,China [3]Quantum Information Center of Southeast University,Nanjing 211100,China [4]Purple Mountain Laboratories,Nanjing 211100,China
出 处:《Science China(Information Sciences)》2020年第10期129-147,共19页中国科学(信息科学)(英文版)
基 金:supported in part by National Key R&D Program of China(Grant No.2020YFB2205503);National Natural Science Foundation of China(Grant Nos.61871115,61501116);Jiangsu Provincial NSF for Excellent Young Scholars(Grant No.BK20180059);Six Talent Peak Program of Jiangsu Province(Grant No.2018DZXX-001);Distinguished Perfection Professorship of Southeast University,Fundamental Research Funds for the Central Universities;Student Research Training Program of Southeast University。
摘 要:Polar codes are one of the most favorable capacity-achieving codes owing to their simple structures and low decoding complexity.Successive cancellation list(SCL)decoders with large list sizes achieve performances very close to those of maximum-likelihood(ML)decoders.However,hardware cost is a severe problem because an SCL decoder with list size L consists of L copies of a successive cancellation(SC)decoder.To address this issue,a stochastic SCL(SSCL)polar decoder is proposed.Although stochastic computing can achieve a good hardware reduction compared with the deterministic one,its straightforward application to an SCL decoder is not well-suited owing to the precision loss and severe latency.Therefore,a doubling probability approach and adaptive distributed sorting(DS)are introduced.A corresponding hardware architecture is also developed.Field programmable gate array(FPGA)results demonstrate that the proposed stochastic SCL polar decoder can achieve a good performance and complexity tradeoff.
关 键 词:SCL polar decoder stochastic computing 2-bit decoding distributed sorting hardware
分 类 号:TN911.22[电子电信—通信与信息系统]
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