一种嵌入式操作系统确定性核间通信机制设计  

Design of Deterministic Inter-core Communication Mechanism for Embedded Operating System

作　　者：朱旭光 李健[1] 包晟临[1] Zhu Xuguang;Li Jian;Bao Shenglin(East China Institute of Computing Technology,Shanghai 201808,China)

机构地区：[1]华东计算技术研究所,上海201808

出　　处：《单片机与嵌入式系统应用》2020年第11期28-31,共4页Microcontrollers & Embedded Systems

摘　　要：为了适应操作系统国产化及高安全操作系统的现实需要,基于飞腾等DSP处理器的缓存机制提出了一种以核上私有内存为中心的多核嵌入式高安全操作系统的核间通信机制设计。为了将其应用到多核嵌入式高安全操作系统中,本文还结合实际操作系统设计中采用的优先级调度方案对该核间通信的确定性做了分析。实验结果表明,该通信机制下,端到端延迟存在一个上限,因此该通信机制的确定性是得到保证的,可以运用到多核高安全嵌入式操作系统中。In order to meet the actual needs of operating system localization and high-security operating system,a multi-core embedded high-security operating system inter-core communication mechanism centered on private memory on the core is proposed,which is based on the cache mechanism of DSP processors such as Feiteng.In order to apply it to the multi-core embedded high-security operating system,this paper also combines the priority scheduling scheme used in the design of our actual operating system to analyze the certainty of inter-core communication.The experiment results show that under this communication mechanism,there is an upper limit for end-to-end delay,so the certainty of the communication mechanism is guaranteed and can be applied to multi-core high-security embedded operating systems.

关 键 词：飞腾处理器 核间通信 DMA 

分 类 号：TP316.2[自动化与计算机技术—计算机软件与理论]