基于级联步进延时的顺序等效采样方法及实现  

Sequential Equivalent Sampling Method and Implementation Based on Cascaded Step Delay

作　　者：李海涛[1] 阮林波[1,2] 田耕 LI Haitao;RUAN Linbo;TIAN Geng(Northwest Institute of Nuclear Technology,Xi'an 710024,China;State Key Lab of Intense Pulsed Radiation Simulation and Effect,Xi'an 710024,China)

机构地区：[1]西北核技术研究院,陕西西安710024 [2]强脉冲辐射环境模拟与效应国家重点实验室,陕西西安710024

出　　处：《自动化仪表》2020年第10期74-77,共4页Process Automation Instrumentation

摘　　要：为提高顺序等效采样率,提出基于级联步进延时的顺序等效采样电路及采样方法。采用可编程延迟线、可编程延迟芯片和现场可编程门阵列(FPGA)等实现采样时钟信号步进延时:利用FPGA控制可编程延迟线和可编程延迟芯片的延时步长和总延时;利用可编程延迟线的粗延时和可编程延迟芯片的细延时相互结合,达到对采样时钟信号进行高精度、大范围的步进延时的目的,实现最小延时步长10 ps、总延时达到512 ns该方法可以广泛应用于顺序等效采样系统。In order to improve the sequential equivalent sampling rate,a sequential equivalent sampling circuit and sampling method based on step delay signal are proposed.Programmable delay line,programmable delay chip and field programmable gate array(FPGA)are used to control the sampling clock signal step delay.The delay step and total delay of programmable delay line and delay chip are controlled by using FPGA,both the coarse delay of programmable delay line and the fine delay of programmable delay chip are combined to achieve high precision and wide range step delay of sampling clock signal.The minimum delay step is 10 ps and the total delay reaches 512 ns.This method can be widely used in sequential equivalent sampling system.

关 键 词：现场可编程门阵列 级联步进延时 可编程延迟线 粗延时步长 可编程延迟芯片 细延时步长 顺序等效采样 

分 类 号：TH331[机械工程—机械制造及自动化]