基于Artix-7 FPGA的三级存储体系设计与实现实验  

Design and Implementation Experiment of Three-level Storage System Based on Artix-7 FPGA

作　　者：秦国锋 秦家豪 邹剑煌 刘鲲 胡岳 QIN Guofeng;QIN Jiahao;ZOU Jianhuang;LIU Kun;HU Yue(Department of Computer Science and Technology,Tongji University,Shanghai 201804,China)

机构地区：[1]同济大学计算机科学与技术系,上海201804

出　　处：《实验室研究与探索》2020年第10期45-49,共5页Research and Exploration In Laboratory

基　　金：2017与2019年教育部-美国DIGILENT公司产学合作协同育人项目(201702015017、201902097011);2017~2019年同济大学实验实践教学改革项目(0800104251、0800104500/015)。

摘　　要：三级存储体系设计与实现实验是计算机系统结构存储体系理论课程的同步配套实验。通过该实验增强学生对理论知识的理解,提升学生的实践开发能力。该实验以学生前期实验完成的基于MIPS指令集的静态和动态流水线CPU成果为基础,在FPGA NEXYS 4开发板上使用SD卡、DDR模块以及片内内存模块构造主存、缓存和辅存的三级存储体系,形成一个可以自启动、自运行的简易计算机系统,为后续其他课程实验贯通,实现完整的计算机系统奠定了基础。The experiment of three-level storage system design and implementation is a synchronous experiment of the storage system theory course of computer architecture.Students can enhance their understanding of theoretical knowledge and enhance their practical development ability with this experiment.This experiment is based on the static and dynamic pipelined CPU achievements on MIPS instruction set,completed by themselves in the previous experiment,and SD cards,DDR modules,and on-chip memory modules are used to construct three levels of main storage,cache,and auxiliary storage on the FPGA NEXYS IV development board to form a simple computer system that can start and run automatically.It lays a foundation for the other following course experiments and the realization of a complete computer system.

关 键 词：三级存储 计算机系统结构 MIPS指令集 

分 类 号：TP306[自动化与计算机技术—计算机系统结构] G642.0[自动化与计算机技术—计算机科学与技术]