CMOS analog and mixed-signal phase-locked loops: An overview  

作　　者：Zhao Zhang 

机构地区：[1]State Key Laboratory of Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China [2]Graduate School of Advanced Science and Engineering,Hiroshima University,1-3-1 Kagamiyama,Higashi-Hiroshima,739-8530,Japan

出　　处：《Journal of Semiconductors》2020年第11期13-30,共18页半导体学报（英文版）

基　　金：supported by the Pioneer Hundred Talents Program,Chinese Academy of Sciences.

摘　　要：CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

关 键 词：phase-locked loop(PLL) charge-pump based PLL(CPPLL) ultra-low-jitter PLL injection-locked PLL(ILPLL) subsampling PLL(SSPLL) sampling PLL(SPLL) 

分 类 号：TN911.8[电子电信—通信与信息系统]