A 12-bit 30-MS/s VCO-based SAR ADC with NOC-assisted multiple adaptive bypass windows  

作　　者：Xiangxin Pan Xiong Zhou Sheng Chang Zhaoming Ding Qiang Li 

机构地区：[1]Institute of Integrated Circuits and Systems,University of Electronic Science and Technology of China,Chengdu 610054,China

出　　处：《Journal of Semiconductors》2020年第11期81-91,共11页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China under Grant 61534002 and Grant 61761136015.

摘　　要：This paper proposes a technique that uses the number of oscillation cycles(NOC)of a VCO-based comparator to set multiple adaptive bypass windows in a 12-bit successive approximation register(SAR)analog-to-digital converter(ADC).The analysis of the number of bit cycles,power and static performance shows that three adaptive bypass windows reduce power consumption,and decrease DNL and have similar INL,compared with the SAR ADC without bypass windows.In addition,a 1-bit split-and-recombination redundancy technique and a general bypass logic digital error correction method are proposed to address the settling issues and optimize the size of the bypass window.This design is implemented in 40 nm CMOS technology.The conversion frequency of the ADC reaches up to 30 MS/s.The ADC achieves an SFDR of 85.35 dB and 11.12-bit ENOB with Nyquist input,consuming 380μW,down from 427μW without multiple adaptive bypass windows,at a 1.1 V supply,resulting in a figure of merit(FoM)of 5.69 fJ/conversion-step.

关 键 词：adaptive bypass window number of oscillation cycles(NOC) offset split-and-recombination redundancy SAR ADC VCO-based comparator 

分 类 号：TN792[电子电信—电路与系统]