一种低码率的LDPC译码器的设计研究  

A low code rate LDPC decoder

作　　者：胡震宇 宋贺伦[2] 郭海波 吴涵 茹占强[2] Hu Zhenyu;Song Helun;Guo Haibo;Wu Han;Ru Zhanqiang(School of Materials Science and Engincering,Shanghai University,Shanghai 200444,China;Suzhou Institute of Nano-Tech and Nano-Eionics,Chinese Academy of Sciences,Suzhou 215123,China)

机构地区：[1]上海大学材料科学与工程学院,上海200444 [2]中国科学院苏州纳米技术与纳米仿生研究所,苏州215123

出　　处：《电子测量技术》2020年第16期62-67,共6页Electronic Measurement Technology

基　　金：国家重点研发计划(2016YFE0129400);“十三五”国家密码发展基金(MMJJ20180112)项目资助。

摘　　要：为满足超晶格密钥分发系统在安全素描过程中对纠错速率和纠错能力的要求,本文给出了一种低码率的LDPC译码器设计。通过理论分析和仿真结果分析相结合的方法,对LDPC译码器的设计方法进行了研究,给出了译码器的FPGA实现方法。用Xilinx公司提供的Vivado软件自带的仿真工具对译码器的功能进行验证,并在Xilinx公司Virtex7系列的XC7VX485T-2FFG1761芯片上综合测试。结果表明,本文实现的译码器最大工作频率为235.76 MHz,在最大迭代次数为20次的情况下,译码器吞吐量可达225.54 Mb/s,能够满足超晶格密钥分发系统的功能实现需求。In order to meet the requirements of error correction rate and error correction capability during the security sketcher process of the superlattice key distribution system, a low code rate LDPC decoder is designed. A method of LDPC decoder and FPGA implementation are given in this article, with theoretical analysis and simulation. Simulation on decoder system with Vivado simulator and the comprehensive test on XC7 VX485 T-2 FFG1761 chip indicate that the throughput capacity of the decoder could reach 225.54 Mb/s when the decoder is at working frequency of 235.76 MHz and maximum iterations number of 20 and meet the needs of the superlattice key distribution system.

关 键 词：低码率 超晶格密钥分发系统 LDPC译码器 FPGA实现 

分 类 号：TN911.22[电子电信—通信与信息系统]