基于DDR2 SDRAM的高速数据缓存技术研究  

Research on high speed data cache technology based on DDR2 SDRAM

作　　者：吕文强 施睿 任勇峰[1] 武慧军[1] Lyu Wenqiang;Shi Rui;Ren Yongfeng;Wu Huijun(National Key Laboratory for Electronic Measurement Technology,North University of China,Taiyuan 030051,China;Key Laboratory of Space Physics,China Academy of Launch Vehicle Technology,Beijing 100076,China)

机构地区：[1]中北大学电子测试技术国家重点实验室,太原030051 [2]中国运载火箭技术研究院空间物理重点实验室,北京100076

出　　处：《电子测量技术》2020年第18期6-10,共5页Electronic Measurement Technology

摘　　要：针对高速数据传输系统中,图像数据采集的速率越来越高,而存储速率有限的问题,提出一种基于DDR2 SDRAM高速数据缓存技术。采用FPGA为主控制器,接收高速图像数据后写入DDR2 SDRAM缓存,在发送周期的空闲时间将数据读出并匹配存储设备的接收速率。为了简化对DDR2 SDRAM的操作,使用ISE软件的存储接口生成工具(MIG)生成DDR2 IP核,实现了在250 MHz时钟下对DDR2 SDRAM的读/写操作,经验证,数据无丢帧无误码,设计稳定可靠。In view of the problem that the image data acquisition rate is higher and higher, but the storage rate is limited in the high-speed data transmission system, a high-speed data cache technology based on DDR2 SDRAM is proposed. FPGA is adopted as the main controller. After receiving high-speed image data, it is written to DDR2 SDRAM cache, and the data is read out and matched with the receiving rate of storage device in the free time of sending cycle.In order to simplify the operation of DDR2 SDRAM, the memory interface generation tool(MIG) of ISE software was used to generate the DDR2 IP core, and the read/write operation of DDR2 SDRAM was realized under the 250 MHz clock. It is proved that the data has no lost frame and no error code, and the design is stable and reliable.

关 键 词：FPGA DDR2 SDRAM DDR2 IP核 高速数据缓存 

分 类 号：TN919.85[电子电信—通信与信息系统]