1.8Vpp 250MS/s低谐波失真流水线ADC  

A 1.8Vpp 250MS/s Pipelined ADC with Low Harmonic Distortion

作　　者：吴柯柯 沈玉鹏 刘家瑞[1] 王志宇[1] 莫炯炯 郁发新[1] WU Ke-ke;SHEN Yu-peng;LIU Jia-rui;WANG Zhi-yu;MO Jiong-jiong;YU Fa-xin(School of Aeronautics and Astronautics,Zhejiang University,Zhejiang,Hangzhou 310027,China)

机构地区：[1]浙江大学航空航天学院,浙江杭州310027

出　　处：《电子学报》2020年第11期2242-2249,共8页Acta Electronica Sinica

基　　金：国家自然科学基金(No.61604128)。

摘　　要：采用40nm CMOS工艺设计了一款在250MS/s采样率下具有1.8Vpp满摆幅和低谐波失真性能的流水线ADC(Analog-to-Digital Converter).针对传统源跟随器结构的输入缓冲器在大摆幅下驱动大采样电容时线性度恶化的问题,采用了改进型电流注入技术和漏端电压自举技术.ADC中实现采样和电荷转移功能的开关采用薄栅器件设计,其工作电压由片上LDO(Low Dropout Regulator)提供,在降低开关寄生和电荷注入的同时保障了器件的可靠性.测试结果表明,对于10.1MHz单音输入,该ADC在-1dBFS下的信噪失真比、无杂散动态范围和总谐波失真分别为68.3dB、76.4dBc、-75.1dBc,在-1.57dBFS下的信噪失真比、无杂散动态范围和总谐波失真分别达68.3dB、80.1dBc、-78.6dBc.This paper presents a 250MS/s pipelined ADC with 1.8Vpp full scale and low harmonic distortion implemented in 40nm CMOS.To reduce the large distortion of the conventional source follower when it drives a large sampling capacitor at a large swing,an improved current injection technique and a drain voltage bootstrapping technique were employed.Switches used for sampling and charge transfer in the ADC were implemented with thin-oxide devices to reduce the parasitic capacitance and charge injection.Moreover,on-chip LDOs were applied to provide safe supply voltages for these switches to protect thin-oxide devices from reliability problems.Test results show that with a 10.1MHz input,the ADC achieves the signal-to-noise and distortion(SNDR)of 68.3dB,the spurious free dynamic range(SFDR)of 76.4dBc and the total harmonic distortion(THD)of-75.1dBc at-1dBFS,and it achieves 68.3dB SNDR,80.1dBc SFDR and-78.6dBc THD at-1.57dBFS.

关 键 词：流水线模数转换器 谐波失真 输入缓冲器 低失真 

分 类 号：TN432[电子电信—微电子学与固体电子学]