基于FPGA的Petri网模拟器设计与实现  

Design and Implementation on Petri Nets Simulator Based on FPGA

作　　者：周韬略 张小军 陈成官 曾庆田 张德学 ZHOU Taolüe;ZHANG Xiaojun;CHEN Chengguan;ZENG Qingtian;ZHANG Dexue(College of Electronic and Information Engineering,Shandong University of Science and Technology,Qingdao 266590,Shandong,China)

机构地区：[1]山东科技大学电子信息工程学院,山东青岛266590

出　　处：《实验室研究与探索》2020年第11期152-156,174,共6页Research and Exploration In Laboratory

基　　金：山东省自然科学基金联合基金(ZR2019LZH001);山东省重点研发计划(2019GGX101066);山东省高等学校青创科技计划(2019KJN020,2019KJN024)。

摘　　要：为加速Petri网的性能测试,设计一个Petri网硬件代码自动生成器,通过Petri网对应的关联矩阵自动生成Verilog文件,可编译下载到FPGA中。对Petri网的硬件模型、库所、变迁进行分析。为模拟Petri网系统中的变迁操作,采用组合逻辑和存储器实现P/T系统,并采用随机策略对资源冲突等情况加以控制。对10个库所、8个变迁的硬件Petri网在Altera Stratix V 5SGXEA7N2F45C2进行综合,工作频率可达300 MHz,可运行1.5×10^8/s步仿真。The paper designs an automated code generator for Petri net,which can generate Verilog code automatically through the incidence matrix of Petri net,and can be compiled and downloaded to FPGA.This paper analyzes the basic hardware model,place and transition of the Petri net.To simulate the transition operation,the paper utilizes combinational logics and memory to realize the P/T system,and adopts random strategy to resolve the resource conflicts.A Petri net with 10 places and 8 transitions is synthesized based on Altera Stratix V 5SGXEA7N2F45C2.It performs 1.5×10^8 steps percent second at 300 MHz.

关 键 词：PETRI网 代码自动生成器 现场可编程逻辑门阵列 VERILOG语言 

分 类 号：TN919[电子电信—通信与信息系统]