应用于高速数据采集系统的超低抖动时钟电路  

Research on Ultra⁃low Jitter Clock Circuit Applied to High Speed Data Acquisition System

作　　者：李海涛[1] 李斌康[1,2] 阮林波 田耕[1,2] 张雁霞 LI Haitao;LI Binkang;RUAN Linbo;TIAN Geng;ZHANG Yanxia(Northwest Institute of Nuclear Technology,Xi'an,710024,China;State Key Laboratory of Intense Pulsed Radiation Simulation and Effect,Xi'an,710024,China)

机构地区：[1]西北核技术研究所,西安710024 [2]强脉冲辐射环境模拟与效应国家重点实验室,西安710024

出　　处：《数据采集与处理》2020年第6期1192-1199,共8页Journal of Data Acquisition and Processing

基　　金：国家自然科学基金(11605141)资助项目;强脉冲辐射环境模拟与效应国家重点实验室(西北核技术研究院)专项经费(SKLIPR1501Z、SKLIPR1502Z)资助项目。

摘　　要：分析了高速数据采集系统对采样时钟抖动的要求,给出了时钟相位噪声和时钟抖动的转换关系;采用HITTITE的HMC1035LP6GE频率综合芯片作为主芯片,设计了时钟生成电路,2500 MHz输出时钟抖动测量值90 fs(整数工作模式,输入频率100 MHz,鉴相频率100 MHz,环路滤波带宽127 kHz,积分区间[10 kHz,10 MHz])。对比时钟生成电路在各种工作模式下的性能,给出了对应的设计指南。This paper analyzes the requirement of sampling clock jitter of high sampling rate and high resolution data acquisition system(DAQ),and gives the relationship between clock phase noise and clock jitter.The HMC1035LP6GE frequency synthesizer chip is used as the main chip of the clock generation circuit with output clock jitter measured as 90 fs(integer mode,2500 MHz output frequency,100 MHz input frequency,phase detector frequency 100 MHz,loop filter bandwidth 127 kHz,integral interval[10 kHz,10 MHz]).The performance of the circuit in various working conditions is compared,and the corresponding design guidelines are given.

关 键 词：高速数据采集 超低时钟抖动 相位噪声 时钟生成 模拟输入带宽 

分 类 号：TN79[电子电信—电路与系统]