面向物联网应用的DRAM与STT-MRAM异构内存系统  

Heterogeneous DRAM and STT⁃MRAM main memory system for IoT applications

作　　者：刘晨吉 陈岚[1,2] 郝晓冉 倪茂[1] 孙浩[1,2] 潘磊 LIU Chenji;CHEN Lan;HAO Xiaoran;NI Mao;SUN Hao;PAN Lei(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049

出　　处：《电子设计工程》2020年第23期1-4,共4页Electronic Design Engineering

基　　金：国家重点研发计划资助(2019YFB2102400);国家重大专项资助(2018ZX03001006-002)。

摘　　要：DRAM内存由于刷新能耗高已无法满足未来应用对物联网终端低能耗的需求。新型非易失存储器具有静态功耗低、存储密度高、读写性能与DRAM相当等特点。其中,STT-MRAM是最有希望取代DRAM成为下一代内存的新型非易失存储器之一。构建DRAM与STT-MRAM异构内存系统,并提出一种基于数据高速缓存访存特征的“分时-并行”异构内存数据迁移算法,在保证内存系统性能的前提下,降低内存系统能耗。使用商用DRAM与STT-MRAM的Verilog模型搭建支持异构内存系统的硬件仿真平台。实验结果表明,文中提出的DRAM与STT-MRAM异构内存系统与DRAM内存相比,性能相当,内存能耗平均降低27%。Due to the high refresh energy consumption of DRAM main memory,it cannot meet the low energy consumption demand of IoT terminals in future applications.The new non⁃volatile memory features low static power consumption,high storage density,and read/write performance comparable to DRAM.Among them,STT⁃MRAM has become one of the most promising new non⁃volatile memories to replace DRAM as the next⁃generation main memory.This paper builds a heterogeneous main memory system with DRAM and STT⁃MRAM and proposes a"time⁃sharing⁃parallel"data migration algorithm based on the data cache access feature.It can reduce main memory energy consumption while ensuring the performance of the main memory.This paper uses commercial DRAM and STT⁃MRAM Verilog model to build a hardware simulation platform that supports heterogeneous main memory system.The results show that the heterogeneous DRAM and STT⁃MRAM main memory system proposed in this paper have comparable performance compared to DRAM,with an average energy consumption reduction of 27%.

关 键 词：物联网终端 STT-MRAM 异构内存 分时-并行 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]