A 16-bit 1 MSPS SAR ADC with foreground calibration and residual voltage shift strategy  

作　　者：Xian Zhang Xiaodong Cao Xuelian Zhang 

机构地区：[1]University of Chinese Academy of Sciences,Beijing 100049,China [2]Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China

出　　处：《Journal of Semiconductors》2020年第12期41-49,共9页半导体学报（英文版）

摘　　要：In this paper,a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter(SAR ADC)is developed by the CMOS 0.25μm process.An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC.The SAR ADC has a chip area of 2.7×2.4 mm^2,and consumes only 100μW at the 2.5 V supply voltage with 100 KSPS.The INL and DNL are both less than 0.5 LSB.

关 键 词：foreground all-digital calibration RS strategy RS-based dither auto-zero comparator SAR ADC 

分 类 号：TN792[电子电信—电路与系统]