超高频RFID标签芯片超低功耗数字基带架构设计  

Ultra Low Power Baseband Architecture Design of UHF RFID Tag IC

作　　者：王家城 郭靖锋 崔臣臣 WANG Jia-cheng;GUO Jing-feng;CUI Chen-chen(Hebei Branch of China Communication System Co.,Ltd;The 54th Research Institute of CETC)

机构地区：[1]中华通信系统有限责任公司河北分公司 [2]中国电子科技集团公司第五十四研究所

出　　处：《中国集成电路》2020年第12期63-68,共6页China lntegrated Circuit

摘　　要：在分析设计超高频RFID标签芯片设计的基础上,数字基带设计在整个芯片设计中最为关键:除了需要满足协议要求进行数据处理外,还需要尽可能的降低功耗来提高整个标签芯片的性能。本文提供了一种数字基带的架构设计,通过模块的合理划分和对基带时钟架构的优化设计,经仿真和功耗分析验证,整个数字基带功耗大约为3.0μw,能够满足无源射频识别芯片的超低功耗的需求。Based on the analysis and design of the UHF RFID tag IC design,the digital baseband design is the most critical in the entire chip design:in addition to meeting the protocol requirements for data processing,it is also necessary to reduce power consumption as much as possible to improve the performance of the entire tag chip.This article provides a digital baseband architecture design.Through reasonable division of modules and optimized clock architecture design,simulation and power analysis verify that the entire digital baseband power consumption is about 3.0μw,which can meet the ultra-high performance of passive radio frequency identification chips.The need for low power consumption.

关 键 词：RFID 标签芯片 数字基带 超低功耗设计 

分 类 号：TN402[电子电信—微电子学与固体电子学] TP391.44[自动化与计算机技术—计算机应用技术]