一种2.4GHz多模块集成CMOS射频前端芯片  

A 2.4GHz multi-module CMOS RF front-end chip

作　　者：陈福栈 甘业兵[1,2,3] 罗彦彬 叶甜春 CHEN Fu-zhan;GAN Ye-bing;LUO Yan-bin;YE Tian-chun(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100049,China;Hangzhou Zhongke Microelectronics Co.,Ltd.,Hangzhou 310053,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100049 [3]杭州中科微电子有限公司,浙江杭州310053

出　　处：《微电子学与计算机》2020年第12期27-32,共6页Microelectronics & Computer

摘　　要：为提升无线通信终端中射频模组的集成度、降低终端的实现成本,基于0.18μm CMOS工艺设计了一款2.4 GHz射频前端芯片,片上集成射频功率放大器(PA)、射频低噪声放大器(LNA)、射频开关、基准源电路及数字控制电路,PA和LNA的阻抗匹配网络均采用片上元件实现.测试结果显示,接收模式下,芯片的增益为11.2 dB,输入\输出回波损耗分别为-5.8 dB及-21.1 dB,IIP3为3.9 dBm;发射模式下,芯片增益达26.8 dB,输入\输出回波损耗分别为-21 dB及-14.2 dB,输出1 dB压缩点为23.5 dBm,峰值PAE达24%.本芯片对于2.4 GHz ISM频段通信系统具备一定的应用价值.To improve the integration density of RF front-end modules and reduce the cost of wireless communication terminals,a 2.4 GHz RF front-end chip is designed and fabricated based on 0.18 um CMOS process.The chip incorporates a power amplifier,a low noise amplifier,a SPST switch,a bandgap circuit and digital control circuit.The impedance matching networks of the PA and the LNA are all implemented on chip.The test results show that in the receiving mode,the chip gain is 11.2 dB,the input output return loss is-5.8 dB and-21.1 dB respectively,and the IIP3 is 3.9 dbM.In the transmission mode,the chip gain is up to 26.8 dB,the input output return loss is-21 dB and-14.2 dB respectively,the output 1 dB compression point is 23.5 dbm,and the peak PAE is up to 24%.The chip possesses application prospect for 2.4 GHz wireless communication systems.

关 键 词：CMOS 射频前端模组 射频功率放大器 射频低噪声放大器 射频开关 

分 类 号：TN432[电子电信—微电子学与固体电子学]