通用总线控制器抗SEU加固设计研究  

Research on theoptimized design of anti-SEU for bus controller chip

作　　者：姜爽 刘诗斌[1] 郭晨光 彭斌 樊旭 JIANG Shuang;LIU Shi-bin;GUO Chen-guang;PENG Bin;FAN Xu(School of Electronics and Information,Northwestern Polytechnical University,Xi'an 710072,China;Beijing Microelectronics Technology Institute,Beijing 100076,China)

机构地区：[1]西北工业大学电子信息学院,西安710072 [2]北京微电子技术研究所,北京100076

出　　处：《微电子学与计算机》2020年第12期81-86,共6页Microelectronics & Computer

摘　　要：随着集成电路制造技术的发展,寄存器和SRAM等存储单元在空间辐射环境中越来越容易受到单粒子翻转(SEU)效应的影响.传统抗SEU加固方法分为工艺加固和设计加固,前者依赖于工艺平台,难度大、周期长,后者仅针对芯片内部特定SEU敏感单元.通过提出一种针对通用总线控制器的芯片级抗SEU加固设计方法,采用冗余编码和刷新技术,可以进一步提高芯片的抗SEU能力;通过划分影响域和添加中断源,便于定位芯片中SEU敏感位置,从而有利于片内刷新操作和后续设计优化.实验结果表明,与传统的辐射加固方法相比,新方法具有更高的辐射可靠性和容错能力.With the development of integrated circuit manufacturing technology,memory cells such as registers and SRAMs are more and more vulnerable to single-event upset(SEU)effect in space radiation environment.There are two traditional anti-SEU methods,i.e.manufacturing process reinforcement and design reinforcement.The former depends on the process platform,which is difficult and has a long period.The latter is only for specific SEU sensitive elements of the chip.By proposing a chip-level anti-SEU reinforcement design method for an universal bus controller chip,using redundant coding and scrubbing methods,the anti-SEU ability of the chip can be further improved.Meanwhile,by dividing influence domain and adding interrupt sources,the chip’s SEU-sensitive elements can be easily identified,which is very convenient for in-system refreshing and subsequent optimization.Verified by SEU experiment,the proposed chip has higher radiation reliability and fault-tolerance than the chip with traditional radiation-hardening methods.

关 键 词：抗SEU 总线控制器 冗余编码 刷新 中断源 

分 类 号：TN4[电子电信—微电子学与固体电子学]