一种降低时钟锁相环抖动的技术研究  

Technique Research for Reducing PLL Jitter

作　　者：冯景 张繁 FENG Jing;ZHANG Fan(YIJIAHE Technology Co.Ltd.,Nanjing Jiangsu 210012,China;Shanghai Nokia Bell Co.Ltd.,Nanjing Jiangsu 210037,China)

机构地区：[1]亿嘉和科技股份有限公司,江苏南京210012 [2]上海诺基亚贝尔股份有限公司,江苏南京210037

出　　处：《通信技术》2020年第12期3116-3121,共6页Communications Technology

摘　　要：高速SERDES串行器内部锁相环的参考时钟有严格的要求,根据某25Gbps数据率SERDES芯片的156.25MHz参考时钟的随机抖动均方差要求,进行锁相环电路设计,根据实测结果,对降低时钟锁相环抖动方案进行技术研究,通过时钟锁相环电路设计优化,从而得到低抖动锁相环优化配置方案。The reference clock of PLL(phase-locked loop)inside the high-speed SERDES Serializer has strict requirements.Based on the requirements of RMS jitter for 156.25MHz reference clock of a SERDES device with 25Gbps datarate,a PLL circuit design is done.According to the test results,a technical method for low PLL jitter is explored,and the PLL circuit design is optimized so as to acquire the most optimized PLL configruation method for low PLL jitter.

关 键 词：SERDES 随机抖动均方差 锁相环 抖动 

分 类 号：TN791[电子电信—电路与系统]