基于CGRA的神经网络高效数据流设计  

Design of Efficient Data Flow of Neural Network Based on CGRA

作　　者：李泽豪 程利甫 蒋仁兴 柳宜川 王琴[1] Li Zehao;Cheng Lifu;Jiang Renxing;Liu Yichuan;Wang Qin(School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University,Shanghai,200240;Shanghai Institute of Aerospace Electronics Technology,Shanghai,201109)

机构地区：[1]上海交通大学电子信息与电气工程学院,上海200240 [2]上海航天电子技术研究所,上海201109

出　　处：《电子测试》2021年第1期67-69,78,共4页Electronic Test

摘　　要：为了充分挖掘阵列结构的并行性,结合脉动阵列思想针对卷积神经网络核心算法设计了一套高效的映射数据流。在基于RTL搭建的仿真环境中,对不同尺寸的卷积核进行了测试,本文所设计的数据流方案的PE平均利用率达到了86%,相对于CPU可以得到652倍的平均加速比。在足够的片上存储资源条件下,所设计的数据流可使CGRA计算单元得到较高的执行效率。In order to fully explore the parallelism of the array structure,a set of efficient neural network core algorithms is designed based on the systolic array idea.Map data flow.In a simulation environment based on RTL,convolution kernels of different sizes were tested.The average utilization rate of PE of the data stream solution designed in this paper reached 86%,which was 614 times faster than the CPU.Under the condition of sufficient on-chip storage resources,the designed data flow can make the CGRA calculation unit get higher execution efficiency.

关 键 词：粗粒度可重构 卷积神经网络加速 脉动阵列 

分 类 号：TP183[自动化与计算机技术—控制理论与控制工程]