高速接口电路发送器的设计  

Design of High-speed Interface Circuit Transmitter

作　　者：吕新为 LV Xinwei(School of Electronic Engineering,Xi'an University of Posts and Telecommunications,Xi'an 710121)

机构地区：[1]西安邮电大学电子工程学院,西安710121

出　　处：《计算机与数字工程》2020年第12期3059-3063,共5页Computer & Digital Engineering

摘　　要：针对高性能模数/数模转换器与FPGA之间的高速数据传输问题,采用数模混合方式设计了高速接口电路发送器,并串转换电路实现并行数据的串化,CML驱动电路以差分形式将串化后的数据进行传输,自适应阻抗匹配电路解决高频信号在传输线上的衰减问题。论文采用SMIC 0.18μm工艺进行电路设计,满足数据高传输速率要求,完成并行数据到串行数据的转换与驱动及传输线特征阻抗匹配,实现高速接口发送器电路的设计。通过仿真验证表明,电路实现10:1并串转换,串行数据的位速率为3.125Gbps,CML驱动电路实现了差分输出,信号输出摆幅500mV,自适应阻抗匹配电路实现了50.05Ω阻抗匹配,偏差为0.1%。In order to solve the problem of high-speed data transmission between the ADC/DAC converter and FPGA,a high-speed interface transmitter circuit is designed.The method of digital-analog hybrid is used to implement the transmitter,the parallel-serial conversion circuit realizes serialization of parallel data,and the CML driving circuit transmits the serialized data in a differential form,and the adaptive impedance matching circuit to solve the problem of transmitting high-frequency signals on the transmission line.Based on the SMIC 0.18μm process,the parallel-to-serial conversion and the drive of serial data and adaptive im⁃pedance matching circuit are all completed.The simulation shows that the circuit realizes 10∶1 parallel-to-serial conversion,the se⁃rial data bit rate is 3.125Gbps.The CML driver circuit realizes differential signal output,the output signal swing is 500mV,and the adaptive impedance matching circuit realizes 50.05Ωimpedance within deviation of 0.1%.

关 键 词：高速接口 并串转换 CML 自适应阻抗匹配 

分 类 号：TN402[电子电信—微电子学与固体电子学]