基于FPGA的DDR2_SDRAM控制器用户接口设计  

The design of DDR2-SDRAM controller user interface based on FPGA

作　　者：韩笑 闫永立 李勇彬 马嘉莉 吴斌 HAN Xiao;YAN Yongli;LI Yongbin;MA Jiali;WU Bin(University of Chinese Academy of Sciences,Beijing 100049,China;Institute of Microelectronics of China Academy of Sciences,Beijing 100029,China;Hunan University,Changsha 410082,China)

机构地区：[1]中国科学院大学,北京100049 [2]中国科学院微电子研究所,北京100029 [3]湖南大学,湖南长沙410082

出　　处：《电子设计工程》2021年第1期168-171,176,共5页Electronic Design Engineering

摘　　要：基于对高带宽数据高速存储的项目需要,选择大容量、成本低、读写速度快的DDR2-SDRAM作为本地存储器,在Stratix系列FPGA开发板上借助硬件描述语言设计了一套控制器用户接口设计方案。该方案基于Synopsys公司出产的DDR2-SDRAM控制器IP核,利用设计的桥接模块用于桥接时序不同的Altera公司提供的硬核PHY层Uniphy。基于AXI3.0总线接口协议,用户接口与控制器之间可支持多数据宽度、多突发长度的高效数据传输。在Intel高性能FPGA StratixⅢ开发板上进行了整体方案的功能设计与系统验证工作,选用的是EP3SL150F1152C2器件,数据读写结果符合预期设计目标。Based on the project needs for high⁃speed storage of high⁃bandwidth data,DDR2-SDRAM with large capacity,low cost,and fast read and write speed was selected as the local memory.A controller user interface solution was designed on the Stratix series FPGA development board using hardware description language.This solution is based on the DDR2-SDRAM controller IP core produced by Synopsys,and the designed bridge module is used to bridge the hard core IP Uniphy provided by Altera with different timing.Based on the AXI3.0 bus interface protocol,the user interface and the controller can support efficient data transmission with multiple data widths and multiple burst lengths.In the Intel high⁃performance FPGA Stratix Ⅲ development board,the functional design and system verification of the overall scheme were performed.The EP3SL150F1152C2 device was selected,and the data reading and writing results met the expected design goals.

关 键 词：用户接口 AXI3.0 FPGA DDR2-SDRAM Uniphy 

分 类 号：TN91[电子电信—通信与信息系统]