基于拉格朗日松弛的多容错专用片上网络拓扑生成  

Lagrangian relaxation based Multi-fault-tolerant topology generation for application-specific Network-on-Chips

作　　者：阮华杰 葛梦柯 陈松[1] RUAN Hua-jie;GE Meng-ke;CHEN Song(University of Science and Technology of China,Hefei 230026,China)

机构地区：[1]中国科学技术大学,安徽合肥230026

出　　处：《微电子学与计算机》2021年第1期12-16,21,共6页Microelectronics & Computer

基　　金：国家自然科学基金(61874102);国家重点研发计划项目(2019YFB2204800)。

摘　　要：随着半导体技术的进步,专用片上网络(ASNoC)成为解决纳米级片上系统通信问题的有效方案.本文提出了一种基于拉格朗日松弛的ASNoC容错拓扑生成方法,可实现大规模ASNoC用户自定义K容错拓扑生成.该ASNoC的容错拓扑生成方法不仅考虑片上网络中可能发生的链路或路由器故障,而且对于用户定义的容错数量K,可以容忍路由器或链路中存在至少K个错误。该方法同时求解IP核映射问题和路由路径分配问题,在满足约束条件下最大程度地降低功耗.实验结果表明,提出的方法显著降低了功耗、物理链路、跳数和运行时间.同时它在可接受的运行时间下实现了大规模ASNoC的容错拓扑生成.With the development of semiconductor technology,application specific network-on-chip(ASNoC)has become an effective solution to the communication problems of nanoscale system-on-chips.This paper presents an ASNoC fault-tolerant topology generation method based on Lagrangian relaxation,which can realize large-scale user-defined K-fault-tolerant topology generation of ASNoC.The fault-tolerant topology generation method of ASNoC not only considers the possible link or router failures in the on-chip network,but also tolerates at least K errors in the router or link for the user-defined fault-tolerant number K.The IP core mapping problem and routing path allocation problem are solved simultaneously,and the power consumption is reduced to the maximum extent under the constraint conditions.The experimental results show that the proposed method significantly reduces power consumption,physical links,hops and running time.Meanwhile,it achieves a large-scale ASNoC fault-tolerant topology with acceptable runtime.

关 键 词：片上网络 专用片上网络 容错 拉格朗日松弛 

分 类 号：TN492[电子电信—微电子学与固体电子学]