基于无冲突访存规则的高性能FFT处理器的设计与实现  

Design and implementation of high performance FFT processor based on conflict-free access rules

作　　者：徐礼晗 景佳[2] 许丁鸿 宋宇鲲[1] XU Li-han;JING Jia;XU Ding-hong;SONG Yu-kun(Institute of VLSI Design IC Design Web-cooperation Research Center of MOE,Hefei University of Technology,Hefei 230009,China;School of Electronic Science&Applied Physics,Hefei University of Technology,Hefei 230009,China)

机构地区：[1]合肥工业大学微电子设计研究所教育部IC设计网上合作研究中心,安徽合肥230009 [2]合肥工业大学电子科学与应用物理学院,安徽合肥230009

出　　处：《微电子学与计算机》2021年第1期57-63,共7页Microelectronics & Computer

基　　金：国家自然科学基金(61874156);国家重点研发计划(2018YFB2202604)。

摘　　要：高性能快速傅里叶变换(FFT)处理器在雷达与通信等实时信号处理系统中具有广泛的应用场景.本文通过优化无冲突访存规则,结合基-2和基-8时域抽取的FFT算法,设计了一种高性能的混合基FFT处理器.该处理器采用基于存储的架构,主要组成单元包括蝶形运算单元,存储单元和控制单元.通过优化无冲突访存规则以及旋转因子生成方案,提高计算速度和硬件效率。在SMIC 40nm标准CMOS工艺下,FFT处理器工作主频超过500 MHz,核心面积为1.76×0.85 mm~2,且计算结果信噪比超过136 dB.在32K点FFT计算任务下,计算速度相比同类型FFT处理器提高约4倍.The high-performance Fast Fourier Transform(FFT)processor has a wide range of application scenarios in real-time signal processingsystems such as radar and communication.In this paper,a high performance FFT processor is designed by optimizing the conflict-free access rules and combining the radix-2 and radix-8 DIT-FFT.The processor employs a Memory-Based architecture,including a butterfly operator unit,a memory unit,and a control unit.The calculation speed and hardware efficiency are improvedImprove calculation speed and hardware efficiency by optimizing Conflict-Free access rules and twiddle factor generation schemes.The proposed processor is implemented on SMIC 40 nm CMOS technology.Simulation results show that the processor can work at over 500 MHz,the core area is1.76×0.85 mm~2,and the SNR is over136 dB or more.Under the 32 K-point FFT calculation task,the calculation speed is about 4 times higher than that of the same type of FFT processor.

关 键 词：快速傅里叶变换 基-8无冲突访存规则 混合基 ASIC 

分 类 号：TN47[电子电信—微电子学与固体电子学]