一种基于并行结构的高速ASIC正交混频器设计  

A High-speed ASIC Quadrature Mixer Design Based on Parallel Structure

作　　者：任凤霞 邵杰 万书芹[1] REN Fengxia;SHAO Jie;WAN Shuqin(The 58th Research Institute,China Electronics Technology Group Corp.,Wuxi,Jiangsu,CHN)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《固体电子学研究与进展》2020年第6期445-450,共6页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(61704161)。

摘　　要：设计了最高采样率为1 GHz的ASIC数字正交混频器。基于正交混频的基本原理,优化了正交混频的算法,优化后的算法节省了硬件资源。为了达到最高采样率的要求,提出了并行结构的电路实现方法。采用MATLAB对正交混频算法进行定点误差分析和频谱分析,并根据MATLAB分析结果设计硬件代码。设计的正交混频器模块应用于ADC电路。基于65 nm CMOS工艺流片后,实际测试结果表明,所设计的正交混频器模块能够满足信噪比和采样率的设计要求。An ASIC quadrature mixer circuit with the highest sample rate of 1 GHz was designed.Based on the basic theory of quadrature mixer,the algorithm of quadrature mixer was optimized,and the optimized algorithm reduced the hardware resources.In order to meet the requirements of the highest sample rate,a circuit implementation method of parallel structure was proposed. MATLAB was used to fixed-point error analysis and the spectrum of analysis on the quadrature mixer. The code of hardware was designed according to the analysis results of MATLAB. The quadrature mixer circuit was integrated in an ADC circuit.Based on 65 nm CMOS process,the actual test results show that the quadrature mixer satisfies the requirements of signal-to-noise ratio and sample rate.

关 键 词：高速ASIC 正交混频 MATLAB 优化算法 硬件设计 

分 类 号：TN432[电子电信—微电子学与固体电子学]