FPGA的星载CAN总线通信系统的设计  

Design of Satellite-borne CAN Bus Communication System Based on FPGA

作　　者：刘志宏 翟耘萱 久元溦 Liu Zhihong;Zhai Yunxuan;Jiu Yuanwei(Beijing Institute of Space Mechanics&Electricity,Beijing 100094,China)

机构地区：[1]北京空间机电研究所,北京100094

出　　处：《单片机与嵌入式系统应用》2021年第2期35-38,43,共5页Microcontrollers & Embedded Systems

摘　　要：本文以A54SX72A反熔丝型FPGA作为主控芯片、以SJA1000作为CAN总线控制器,提出一种星载CAN总线通信系统的设计方案,分别对不同类型的总线通信任务进行合理分类并针对性处理,通过外设MRAM协助完成部分数据存储与读取,实现总线通信系统指令接收、解析、存储和响应功能。本文首先介绍了星载CAN总线通信系统的硬件环境,随后结合FPGA的实际设计对CAN总线通信的工作状态和工作流程进行描述,最后详述了系统的FPGA设计思路。设计方案分别通过了基于ModelSim和硬件专用测试设备的验证,验证结果表明功能正确,性能良好,可为后续型号产品的研制提供参考。This paper gives a design of CAN processer which uses A54SX72A,a kind of antifuseFPGA,as the main control chip and SJA1000 as the controller of CAN bus.The system offers special solutions for different data types,and MRAM is used to store and retrieve the broadcast data.Firstly,thepaperintrduces the hardware environment of satellite-borne CAN bus system.Subsequently,the classification of work status and workflows of different data are raised.Finally,the paper gives detailed description of design solution of FPGA system.The design is verified by ModelSim and hardware device,the result of the verification indicates that the system is implemented correctly with high performance,and informs the design of future missions and instruments.

关 键 词：FPGA A54SX72A CAN总线 SJA1000 

分 类 号：TP702[自动化与计算机技术—检测技术与自动化装置]