QC_LDPC高速译码器的优化与实现  

Optimization and Implementation of Quasi-Cyclic Low-Density Parity-Check Codes High Speed Decoder

作　　者：薛丽 Xue Li(Southwest China Electronic Technology Institute,Sichuan Chendu 610036)

机构地区：[1]中国西南电子技术研究所,四川成都610036

出　　处：《电子质量》2021年第1期39-42,46,共5页Electronics Quality

摘　　要：准循环低密度校验码(QC_LDPC码)以其优越的性能及较低的编译码复杂度得到了广泛的应用,目前,准循环LDPC码已成为CCSDS深空通信的方案之一。如何在FPGA上实现高速译码,则是QC_LDPC码应用的一个焦点。该文简单介绍了QC_LDPC码的译码实现过程,设计提出了快速处理校验节点迭代过程的实现方法,可以大大加快译码过程,尤其当校验矩阵行重较大时,有利于高速译码。Quasi-cyclic low-density parity-check(QC_LDPC)codes has been widely used because of its superior performance and low encoding and decoding complexity.At present,Quasi-cyclic low-density parity-check code become one of the schemes of CCSDS deep space communication.How to realize high speed decoding on FPGA is the key problem of the codes application.This paper briefly introduces he decoding process of QC_LDPC codes,a method of fast processing the iterative process of check nodes is proposed,which can greatly speed up the decoding process,especially when the check matrix has a large row weight.

关 键 词：QC_LDPC码 最小和算法 高速译码器 

分 类 号：TN764[电子电信—电路与系统] TN702