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作 者:杨坤 蒋林 谢晓燕 邓军勇 刘新闯 胡传瞻 YANG Kun;JIANG Lin;XIE Xiao-yan;DENG Jun-yong;LIU Xin-chuang;HU Chuan-zhan(School of Electronic Engineering,Xi’an University of Posts&Telecommunications,Xi’an 710121;Laboratory of Integrated Circuit,Xi’an University of Science and Technology,Xi’an 710054;School of Computer Science,Xi’an University of Posts&Telecommunications,Xi’an 710121,China)
机构地区:[1]西安邮电大学电子工程学院,陕西西安710121 [2]西安科技大学集成电路实验室,陕西西安710054 [3]西安邮电大学计算机学院,陕西西安710121
出 处:《计算机工程与科学》2021年第2期354-361,共8页Computer Engineering & Science
基 金:国家自然科学基金(61772417,61834005,61802304,61602377,61634004);陕西省科技统筹创新工程(2016KTZDGY02-04-02);陕西省重点研发计划(2017GY-0609)。
摘 要:基于视频阵列处理器高效视频编码HEVC实现中,HEVC灵活的编码块增加了率失真优化算法硬件实现的难度,难以实现阵列规模和不同块的灵活切换。针对这一问题,提出一种动态可重构的率失真优化实现方法。基于上下文切换的动态重构机制,完成不同规模、不同块大小算法之间的灵活切换,并以率失真优化算法作为帧内模式选择的判别依据,实现帧内预测的模式重构。实验结果表明,与专用硬件实现的率失真优化算法相比,在算法灵活切换的同时,硬件面积减少了8.2%,算法执行的时钟周期数减少了16.5%。In the implementation based on video array processor,the flexible coding blocks of High Efficiency Video Coding(HEVC)increase the difficulty of hardware implementation of the rate-distortion optimization algorithm,and it is difficult to realize the array size and flexible switching of different blocks.Aiming at this problem,a dynamic reconfigurable implementation method of rate-distortion optimization is proposed.The dynamic reconfiguration mechanism based on context switching completes the flexible switching among algorithms of different sizes and different block sizes,and uses the rate-distortion optimization algorithm as the basis of discriminating the intra-mode selection to realize the intra-prediction mode reconfiguration.Experimental results show that,compared with the rate-distortion optimization algorithm implemented by dedicated hardware,when the algorithm is flexibly switched,the hardware area is reduced by 8.2%,and the number of clock cycles of algorithm execution is reduced by 16.5%.
关 键 词:动态可重构 高效视频编码 率失真优化 阵列处理器
分 类 号:TP302[自动化与计算机技术—计算机系统结构]
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