基于CMOS40nm工艺三维阻变存储器的自适应读写电路设计  

Design of adaptive read-write circuit based on CMOS 40 nm process 3D resistive memory

作　　者：高琪 田文杰[1] 陈福彬[1] 张锋[2] GAO Qi;TIAN Wenjie;CHEN Fubin;ZHANG Feng(Sensors Key Laboratory,Beijing Information Science and Technology University,Beijing 100101,China;Key Laboratory of Microelectronics Devices and Integrated Technology,Institute of Microelectronics of the Chinese Academy of Sciences,Beijing 100029,China)

机构地区：[1]北京信息科技大学传感器重点实验室,北京100101 [2]中国科学院微电子研究所微电子器件与集成技术重点实验室,北京100029

出　　处：《电子设计工程》2021年第3期1-6,共6页Electronic Design Engineering

基　　金：国家重点研发计划(2018YFB0407500)。

摘　　要：针对三维阻变存储器的材料特性和器件结构,采用了一种基于CMOS 40 nm工艺的自适应读写电路,该电路具有高可靠性、低功耗以及反馈自适应的技术特点。通过多层译码结构、写入验证电路、小信号灵敏放大读出电路以及自适应控制机制,可以实现三维阻变存储器的高速低功耗的读写以及多种不同阻态的写入,从而有效解决了阻变存储器写操作过程中存在的过写入问题,大幅提高了三维阻变存储器写入和读出的成功率。根据仿真结果分析,带有反馈机制的写入电路可以实现90%以上的写入成功率。在1.1 V的工作电压下,写入功耗仅为99.752μW/bit。Aiming at the material characteristics and device structure of the three-dimensional resistive memory,an adaptive read-write circuit based on CMOS 40 nm process is adopted,which has the technical characteristics of high reliability,low power consumption and feedback adaptation.Through multi-layer decoding structure,write verification(write-verify)circuit,small signal sensitive amplification readout circuit and adaptive control mechanism,the high speed and low power consumption reading and writing of resistive memory based on 3D multi-layer structure and the writing of many different resistance states can be realized,thus effectively solving the problem of overwriting in the writing operation of resistive memory,thus greatly improving the success rate of writing and readout of 3D resistive memory.According to the simulation results,the write circuit with feedback mechanism can finally achieve a write success rate of more than 90%,and the write power consumption is only 99.752μW/bit at 1.1 V operating voltage.

关 键 词：三维阻变存储器 不同阻态的写入 自适应读写电路 低功耗 高写入率 

分 类 号：TN432[电子电信—微电子学与固体电子学]