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作 者:梁艳 LIANG Yan(College of Mechanical and Electrical Engineering,Shanghai Jian Qiao University,Shanghai 201306,China)
出 处:《微电子学与计算机》2021年第2期47-51,共5页Microelectronics & Computer
摘 要:为了提高物理层下行控制信道(Physical Downlink control channel PDCCH)极化码译码的吞吐率,降低复杂度,减少第五代无线通信终端的设计面积,本文提出了一种适用于半导体芯片设计的极化码译码算法.鉴于PDCCH携带的控制信息需要盲解的特性,本文采用分布式循环冗余校验辅助串行抵消表的方法研究了PDCCH的Polar译码过程.通过路径排序和分布式CRC校验比特早停功能,对路径进行优化选择,简化了Polar译码的复杂度;提出并行模块组的改进译码方法减小了芯片设计面积.仿真结果表明该方法不仅降低了复杂度,而且保证了译码性能.To enhance the throughput of Physical Downlink control channel(PDCCH)Polar decoded and to reduce the complexity of the 5th wireless communication terminal equipment,this paper proposes a Polar decoder algorithm suitable for semiconductor chip design.In view of the characteristics of PDCCH,the decoding of PDCCH Polar is studied by using the method of CRC-Aided successive cancellation method.Polar decoding complexity was simplified by optimizing the path selection through path sorting and distributed CRC early stop function.And the throughput is enhanced by using the method of paralleled processing for chip design.Simulation results show that this method not only reduces the complexity,but also guarantees the decoding performance.
关 键 词:物理层下行控制信道 极化码 分布式循环冗余校验辅助串行抵消表 路径度量 早停
分 类 号:TN911.22[电子电信—通信与信息系统]
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