一种阵列式版图布局的低温度系数CMOS带隙基准电压源  

A Low Temperature Coefficient CMOS Bandgap Reference Voltage Source with Transistor-Array Layout

作　　者：王鹏飞 刘博 段文娟 张立文 张金灿 Wang Pengfei;Liu Bo;Duan Wenjuan;Zhang Liwen;Zhang Jincan(Electrical Engineering College,Henan University of Science and Technology,Luoyang 471023,China)

机构地区：[1]河南科技大学电气工程学院,河南洛阳471023

出　　处：《半导体技术》2021年第1期24-29,共6页Semiconductor Technology

基　　金：国家自然科学基金资助项目(61704049,61804046);河南省科技厅重点科技攻关项目(192102210087,202102210322)。

摘　　要：设计了一款低温度系数的自偏置CMOS带隙基准电压源电路,分析了输出基准电压与关键器件的温度依存关系,实现了低温度系数的电压输出。后端物理设计采用多指栅晶体管阵列结构进行对称式版图布局,以压缩版图面积。基于65 nm/3.3 V CMOS RF器件模型,在Cadence IC设计平台进行原理图和电路版图设计,并对输出参考电压的精度、温度系数、电源抑制比(PSRR)和功耗特性进行了仿真分析和对比。结果表明,在3.3 V电源和27℃室温条件下,输出基准电压的平均值为765.7 mV,功耗为0.75μW;在温度为-55~125℃时,温度系数为6.85×10~(-6)/℃。此外,输出基准电压受电源纹波的影响较小,1 kHz时的PSRR为-65.3 dB。A self-bias CMOS bandgap reference voltage source circuit with low temperature coefficient was designed.The dependence relationship of the output reference voltage and the temperature of the key devices was analyzed,and the voltage output with the low temperature coefficient was realized.In back-end physical design,a multi-finger transistor-array structure was used for symmetrical layout to compress the layout area.Based on 65 nm/3.3 V CMOS RF device model,the circuit and its layout were designed on Cadence IC platform.The precision of the output reference voltage,the temperature coefficient,the power supply rejection ratio(PSRR)and the power consumption characteristics were simulated and compared.The results show that under the conditions of 3.3 V power supply and 27℃room temperature,the average value of the output reference voltage is 765.7 mV,and the power consumption is 0.75μW.At the temperature of-55-125℃,the temperature coefficient is 6.85×10-6/℃.In addition,the output reference voltage is less affected by the power ripple,the PSRR is-65.3 dB at 1 kHz.

关 键 词：互补金属氧化物半导体(CMOS) 带隙基准电压源 低温度系数 亚阈值区 晶体管阵列版图 

分 类 号：TN432[电子电信—微电子学与固体电子学]