基于LVDS的高速数据回读系统设计  

Design of High-Speed Data Readback System Based on LVDS

作　　者：薛栋 李杰 张德彪[1,2] 王瀚 XUE Dong;LI Jie;ZHANG De-biao;WANG Han(School of Instrument and Electronics,North University of China,Taiyuan 030051,China;Key Laboratory of Instrumentation Science&Dynamic Measurement(North University of China),Ministry of Education,Taiyuan 030051,China)

机构地区：[1]中北大学仪器与电子学院,山西太原030051 [2]中北大学仪器科学与动态测试教育部重点实验室,山西太原030051

出　　处：《中北大学学报（自然科学版）》2021年第2期135-139,共5页Journal of North University of China(Natural Science Edition)

基　　金：国家自然科学基金资助项目(61973280)。

摘　　要：针对某型号弹体在发射和飞行过程中被测参数信号存在脉宽极窄的现象,其内置离线式采集系统在设计时会采用高采样率的模数转换器(ADC),但存在固态存储器(Flash)最终存储的数据量太大、现有回读系统速率慢、回读时间过长、靶场实验无法继续进行等问题.基于此,设计了一种可以将数据高速回读的系统.系统使用现场可编辑门阵列(FPGA)作为主控模块,利用FPGA内部资源搭建低电压差分信号(LVDS)接口用于数据回读;使用Visual Studio编写上位机,完成指令和数据的交互,实现数据的及时回读.实验结果表明,该系统回读速率达100 MB/s,且无误码、丢帧现象.The pulse width of the measured parameter signal of a certain type of projectile body is very narrow in the process of launching and flying,the off-line acquisition system used high sampling rate analog to digital converter(ADC)at design time,there were problems that solid-state memory(Flash)finally stored too much data,the existing readback system speed was too slow,the readback time was too long,and the range experiment cound not continue.Based on the above issues,a high-speed read-back system was designed.The system used field programmable gate array(FPGA)as the main control module,and used the internal resources of FPGA to build a low-voltage differential signal(LVDS)interface for data readback.Used visual studio to compile the host computer,complete the interaction of instructions and data,and realize the timely readback of data.Experimented verifies that the readback rate can reach 100 MB/s without error or frame loss.

关 键 词：低电压差分信号(LVDS) 高速数据回读 现场可编辑门阵列(FPGA) 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]