MHAL硬件抽象层数据流的分级调度设计  

Design of Hierarchical Scheduling Mechanism for Hardware Abstraction Layer Data Stream

作　　者：路小超 Lu Xiaochao(Southwest China Institute of Electronic Technology,Chengdu 610036,China)

机构地区：[1]中国西南电子技术研究所,成都610036

出　　处：《单片机与嵌入式系统应用》2021年第4期68-70,80,共4页Microcontrollers & Embedded Systems

摘　　要：分析MHAL硬件抽象层的技术规范,针对MHAL硬件抽象层在数据调度方面的局限性,结合数据帧的优先级业务属性设计了具有实时数据传输保障的调度。按照优先级将数据帧进行队列管理,完成硬件抽象层数据流的分级调度。测试结果表明,该设计能够实现MHAL硬件抽象层数据流的分级调度,提高了MHAL硬件抽象层数据调度的灵活性,对推进SCA软件通信体系架构在嵌入式系统中的应用研究具有积极意义。A scheduling design with real-time data transmission guarantee is designed for the limitation of modem hardware abstraction layer(MHAL)in data scheduling by analyzing the technical specification of MHAL hardware abstraction layer and combing with the priority business attribute of data frame.Queue management is applied to data frames according to the priority to complete the hierarchical scheduling of the data flow in the hardware abstraction layer.The test results show that this design can realize the hierarchical scheduling of MHAL hardware abstraction layer data flow,improve the flexibility of MHAL hardware abstraction layer data scheduling,and have positive significance for promoting the application research of software communication architecture(SCA)in embedded system.

关 键 词：MHAL 优先级 队列管理 分级调度 SCA 

分 类 号：TN802[电子电信—信息与通信工程] TN923