基于JESD204B的1 GS/s、16-bit数据采集系统研究  

Research on 1 GS/s,16-bit data acquisition system based on JESD204B

作　　者：李海涛[1,2] 李斌康 田耕[1,2] 阮林波 张雁霞[1,2] Li Haitao;Li Binkang;Tian Geng;Ruan Linbo;Zhang Yanxia(Northwest Institute of Nuclear Technology,Xi′an 710024,China;State Key Lab of Intense Pulsed Radiation Simulation and Effect,Xi′an 710024,China)

机构地区：[1]西北核技术研究所,陕西西安710024 [2]强脉冲辐射环境模拟与效应国家重点实验室,陕西西安710024

出　　处：《电子技术应用》2021年第4期126-131,共6页Application of Electronic Technique

摘　　要：采用“ADC+FPGA”的架构,设计了1 GS/s、16-bit高速高精度数据采集系统,实现了大动态范围(>1000倍)信号的单信道测量功能。研究采用周期sysref和脉冲sysref两种模式,分别建立了稳定连接的、具有确定性延迟的JESD204B连接,对比了两种模式下的采样数据频谱差别,结合硬件设计、固件设计的注意事项,推荐采用周期sysref建立JESD204B连接。研究分析采样数据的时域波形和频率谱密度,验证了ADC芯片内部包含4个片上ADC通道的结论。The paper adopts the architecture of"ADC+FPGA",designs and develops a 1 GS/s,16-bit high-speed and high-precision data acquisition system(DAS),which realized the purpose of using a single channel to measure large dynamic range(DR>1000)signals.The study uses two sysref modes,which are periodic sysref mode and pulse sysref mode,to establishe a stable JESD204B link with a deterministic delay.The differences in the sampled data spectrum between the two modes is presented,and the considerations of hardware design and firmware design are given.The paper recommends that the periodic sysref mode be used to establish JESD204B link.By analyzing the time-domain waveform and frequency spectrum of the sampled data,the conclusion that the ADC chip contains 4 on-chip ADC channels is verified.

关 键 词：数据采集系统 JESD204B 确定性延迟 周期sysref 脉冲sysref 相干采样 

分 类 号：TN6[电子电信—电路与系统]