基于差分编码技术的12.5Gbit/s高速SerDes发射机  

A 12.5 Gbit/s High Speed SerDes Transmitter Based on Differential Encoding Technology

作　　者：彭嘉豪 李儒章[2] 付东兵[2] 丁一[2] 杨虹[1] PENG Jiahao;LI Ruzhang;FU Dongbing;DING Yi;YANG Hong(College of Optoelectronic Engineering,Chongqing University of Posts and Telecommunications,Chongqing 40065,P.R.China;Science and Technology on Analog Integrated Circuit Laboratory,Chongqing 400060,P.R.China)

机构地区：[1]重庆邮电大学光电工程学院,重庆400065 [2]模拟集成电路国家重点实验室,重庆400060

出　　处：《微电子学》2021年第1期85-90,共6页Microelectronics

基　　金：模拟集成电路国家重点实验室基金资助项目(614280205020417)。

摘　　要：研究并设计了一种基于差分编码技术的12.5 Gbit/s高速SerDes发射机。该电路由并串转换模块、去加重控制模块和驱动模块组成。驱动模块采用电流模逻辑异或门结构,动态负载的加入可以在降低功耗的同时实现与传输线的阻抗匹配。首次提出在并串转换模块中加入差分编码电路的解决方案,以保证原码输出,从而使数据在发射机内完成差分编解码的过程。后仿真结果表明,发射机数据传输速度达到12.5 Gbit/s。此时发射机整体功耗为39 mW,输出总抖动为0.05 UI,远小于JESD204B标准所要求的0.3 UI。A 12.5 Gbit/s high speed SerDes transmitter based on differential encoding technology was researched and designed. This circuit was mainly composed of a parallel-serial conversion module, a de-emphasis control module and a drive module. The driving module adopted a current mode logic XOR gate structure, and the addition of dynamic load could reduce the power consumption and achieve impedance matching with the transmission line. In order to ensure the original code output, a solution for adding a differential encoding circuit to the parallel-serial conversion module was proposed for the first time, so that the process of differential encoding and decoding with the data could be completed in the transmitter. The post simulation results showed that the data transmission speed of the transmitter reached 12.5 Gbit/s. Meanwhile, the overall power consumption of the transmitter was 39 mW, and the total output jitter was 0.05 UI, which was far less than the 0.3 UI required by the JESD204 B standard.

关 键 词：差分编码 高速SerDes 电流模逻辑异或门 动态负载 

分 类 号：TN432[电子电信—微电子学与固体电子学]